5秒后页面跳转
SN74LVC823ADB PDF预览

SN74LVC823ADB

更新时间: 2024-11-17 22:16:19
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
14页 295K
描述
9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74LVC823ADB 数据手册

 浏览型号SN74LVC823ADB的Datasheet PDF文件第2页浏览型号SN74LVC823ADB的Datasheet PDF文件第3页浏览型号SN74LVC823ADB的Datasheet PDF文件第4页浏览型号SN74LVC823ADB的Datasheet PDF文件第5页浏览型号SN74LVC823ADB的Datasheet PDF文件第6页浏览型号SN74LVC823ADB的Datasheet PDF文件第7页 
SN74LVC823A  
9-BIT BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS305IMARCH 1993REVISED FEBRUARY 2005  
FEATURES  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.9 ns at 3.3 V  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
1Q  
Typical VOLP (Output Ground Bounce)  
22 2Q  
<0.8 V at VCC = 3.3 V, TA = 25°C  
3Q  
4Q  
5Q  
6Q  
21  
20  
19  
18  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
17 7Q  
16 8Q  
15 9Q  
3.3-V VCC  
)
9D 10  
Ioff Supports Partial-Power-Down Mode  
Operation  
CLR  
GND  
CLKEN  
CLK  
11  
12  
14  
13  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is  
particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and  
working registers.  
With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high  
transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. This device has  
noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low,  
independently of the clock.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC823ADW  
TOP-SIDE MARKING  
Tube of 25  
SOIC – DW  
LVC823A  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 60  
SN74LVC823ADWR  
SN74LVC823ANSR  
SN74LVC823ADBR  
SN74LVC823APW  
SOP – NS  
LVC823A  
LC823A  
SSOP – DB  
–40°C to 85°C  
TSSOP – PW  
Reel of 2000  
Reel of 250  
Reel of 2000  
SN74LVC823APWR  
SN74LVC823APWT  
SN74LVC823ADGVR  
LC823A  
TVSOP – DGV  
LC823A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

与SN74LVC823ADB相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC823ADBLE TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADBR TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADBRE4 TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADBRG4 TI

获取价格

LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74LVC823ADGVR TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADGVRE4 TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADW TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADWE4 TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADWG4 TI

获取价格

LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74LVC823ADWR TI

获取价格

9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS