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SN74LVC74DR PDF预览

SN74LVC74DR

更新时间： 2024-10-02 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
6页 86K
描述
Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset 14-SOIC -40 to 85

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SN74LVC74DR 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, SO-14针数：14
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.28Is Samacsys：N
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G14
长度：8.65 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：100000000 Hz
最大I（ol）：0.024 A位数：1
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：6.5 ns
传播延迟（tpd）：6.5 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：100 MHzBase Number Matches：1

SN74LVC74DR 数据手册

 浏览型号SN74LVC74DR的Datasheet PDF文件第2页浏览型号SN74LVC74DR的Datasheet PDF文件第3页浏览型号SN74LVC74DR的Datasheet PDF文件第4页浏览型号SN74LVC74DR的Datasheet PDF文件第5页浏览型号SN74LVC74DR的Datasheet PDF文件第6页 
SN74LVC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
SCAS287B – JANUARY 1993 – REVISED JULY 1995  
D, DB, OR PW PACKAGE  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
(TOP VIEW)  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
1CLR  
1D  
1CLK  
1PRE  
1Q  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
2D  
2CLK  
2PRE  
2Q  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
1Q  
GND  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
2Q  
8
OLP  
= 3.3 V, T = 25°C  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Inputs Accept Voltages to 5.5 V  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V  
operation.  
CC  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input may be changed without affecting the levels at the outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN74LVC74 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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