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SN74LVC821APW

更新时间： 2024-09-29 22:16:19
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 141K
描述
10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74LVC821APW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：0.77
Is Samacsys：N控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：10功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：7.3 ns
传播延迟（tpd）：8.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74LVC821APW 数据手册

 浏览型号SN74LVC821APW的Datasheet PDF文件第2页浏览型号SN74LVC821APW的Datasheet PDF文件第3页浏览型号SN74LVC821APW的Datasheet PDF文件第4页浏览型号SN74LVC821APW的Datasheet PDF文件第5页浏览型号SN74LVC821APW的Datasheet PDF文件第6页浏览型号SN74LVC821APW的Datasheet PDF文件第7页 
SN74LVC821A  
10-BIT BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS304F – MARCH 1993 – REVISED JUNE 1998  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
OE  
1D  
2D  
3D  
4D  
1
24  
V
CC  
= 3.3 V, T = 25°C  
CC  
A
2
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
3
OHV  
OH  
= 3.3 V, T = 25°C  
4
CC  
A
5
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
5D  
6
3.3-V V  
)
7
18  
17  
16  
15  
14  
13  
6D  
6Q  
CC  
8
7D  
8D  
9D  
10D  
GND  
7Q  
8Q  
9Q  
10Q  
CLK  
Power Off Disables Outputs, Permitting  
Live Insertion  
9
10  
11  
12  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports,  
bidirectional bus drivers with parity, and working registers.  
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the  
device provides true data at the Q outputs.  
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can  
be entered while the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVC821A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74LVC821APW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC821ADWR TI

完全替代

 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADBR TI

完全替代

 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADW TI

完全替代

 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74LVC821APWE4 TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-TSSOP -40 to 85
SN74LVC821APWR TI

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 		10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821APWT TI

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 		10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821APWTG4 TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
SN74LVC821DB TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24
SN74LVC821DBLE TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-SSOP -40 to 85
SN74LVC821DW TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-SOIC -40 to 85
SN74LVC821DWR TI

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 		暂无描述
SN74LVC821PWLE TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-TSSOP -40 to 85
SN74LVC823A TI

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 		9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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