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SN74LVC821APWR

更新时间： 2024-11-21 05:16:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
16页 466K
描述
10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVC821APWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.77Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：UNIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
湿度敏感等级：1位数：10
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：7.3 ns传播延迟（tpd）：8.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

SN74LVC821APWR 数据手册

 浏览型号SN74LVC821APWR的Datasheet PDF文件第2页浏览型号SN74LVC821APWR的Datasheet PDF文件第3页浏览型号SN74LVC821APWR的Datasheet PDF文件第4页浏览型号SN74LVC821APWR的Datasheet PDF文件第5页浏览型号SN74LVC821APWR的Datasheet PDF文件第6页浏览型号SN74LVC821APWR的Datasheet PDF文件第7页 
SN74LVC821A  
10-BIT BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005  
FEATURES  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.3 ns at 3.3 V  
OE  
1D  
2D  
1
24  
23  
22  
V
CC  
2
1Q  
2Q  
Typical VOLP (Output Ground Bounce)  
3
<0.8 V at VCC = 3.3 V, TA = 25°C  
3D  
4D  
4
21 3Q  
20 4Q  
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
5
6
19  
18  
17  
16  
15  
14  
13  
5D  
6D  
7D  
8D  
5Q  
6Q  
7Q  
8Q  
7
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
8
3.3-V VCC  
)
9
10  
11  
12  
9D  
10D  
GND  
9Q  
10Q  
CLK  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
DESCRIPTION/ORDERING INFORMATION  
This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports,  
bidirectional bus drivers with parity, and working registers.  
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the  
device provides true data at the Q outputs.  
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can  
be entered while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC821ADW  
TOP-SIDE MARKING  
Tube of 25  
SOIC – DW  
LVC821A  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 60  
SN74LVC821ADWR  
SN74LVC821ANSR  
SN74LVC821ADBR  
SN74LVC821APW  
SOP – NS  
LVC821A  
LC821A  
SSOP – DB  
–40°C to 85°C  
TSSOP – PW  
TVSOP – DGV  
Reel of 2000  
Reel of 250  
Reel of 2000  
SN74LVC821APWR  
SN74LVC821APWT  
SN74LVC821ADGVR  
LC821A  
LC821A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...16

中文翻译

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SN74LVC821APWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC821APW TI

类似代替

 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADW TI

类似代替

 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74LVC821APWT TI

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SN74LVC821APWTG4 TI

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SN74LVC821DBLE TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-SSOP -40 to 85
SN74LVC821DW TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-SOIC -40 to 85
SN74LVC821DWR TI

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 		暂无描述
SN74LVC821PWLE TI

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 		10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-TSSOP -40 to 85
SN74LVC823A TI

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 		9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823A_08 TI

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 		9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC823ADB TI

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 		9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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