SN74LVC821A

更新时间： 2024-10-01 22:16:19

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
9页	141K
描述
10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74LVC821A 数据手册

SN74LVC821A

10-BIT BUS-INTERFACE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS304F – MARCH 1993 – REVISED JUNE 1998

DB, DW, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

23 1Q

22 2Q

21 3Q

20 4Q

19 5Q

Typical V

> 2 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Supports Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

10D

GND

10Q

CLK

Power Off Disables Outputs, Permitting

Live Insertion

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V

operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports,

bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the

device provides true data at the Q outputs.

A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines

without interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC821A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN74LVC821A相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC821A_08	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADB	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADBLE	TI	获取价格	10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-SSOP -40 to 85
SN74LVC821ADBR	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADBRE4	TI	获取价格	LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74LVC821ADGVR	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADGVRE4	TI	获取价格	10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-TVSOP -40 to 85
SN74LVC821ADGVRG4	TI	获取价格	LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TVSOP-24
SN74LVC821ADW	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADWR	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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