5秒后页面跳转
捷配首页

Datasheet > SN74LVC74AQPWRQ1
SN74LVC74AQPWRQ1 PDF预览

SN74LVC74AQPWRQ1

更新时间： 2024-11-19 11:07:59
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
11页 222K
描述
汽车类具有清零和预设功能的双路上升沿 D 类触发器 | PW | 14 | -40 to 125

阅读下载

中文翻译

获取价格

SN74LVC74AQPWRQ1 数据手册

 浏览型号SN74LVC74AQPWRQ1的Datasheet PDF文件第2页浏览型号SN74LVC74AQPWRQ1的Datasheet PDF文件第3页浏览型号SN74LVC74AQPWRQ1的Datasheet PDF文件第4页浏览型号SN74LVC74AQPWRQ1的Datasheet PDF文件第5页浏览型号SN74LVC74AQPWRQ1的Datasheet PDF文件第6页浏览型号SN74LVC74AQPWRQ1的Datasheet PDF文件第7页 
SN74LVC74A-Q1  
www.ti.com ...................................................................................................................................................... SCES481C–AUGUST 2003–REVISED APRIL 2008  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
1
FEATURES  
•
Qualified for Automotive Applications  
D OR PW PACKAGE  
(TOP VIEW)  
•
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1CLR  
1D  
1
2
3
4
5
6
7
14 VCC  
13  
12  
11  
10  
9
2CLR  
2D  
•
•
•
•
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.2 ns at 3.3 V  
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
Typical VOLP (Output Ground Bounce) <0.8 V at  
VCC = 3.3 V, TA = 25°C  
1Q  
8
GND  
2Q  
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC74A-Q1 dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Reel of 2500  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC74AQDRQ1  
TOP-SIDE MARKING  
LVC74AQ  
LVC74AQ  
SOIC – D  
–40°C to 125°C  
TSSOP – PW  
SN74LVC74AQPWRQ1  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...11

中文翻译

下载PDF

SN74LVC74AQPWRQ1 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC74AQPWRG4Q1 TI

完全替代

 汽车类具有清零和预设功能的双路上升沿 D 类触发器 | PW | 14 | -40 to
V62/04669-01YE TI

完全替代

 DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC74AQPWREP TI

完全替代

 DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

与SN74LVC74AQPWRQ1相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC74ARGYR TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74LVC74ARGYRG4 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74LVC74D TI

获取价格

 		Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset 14-SOIC -40 to 85
SN74LVC74DBLE TI

获取价格

 		Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset 14-SSOP -40 to 85
SN74LVC74DBR TI

获取价格

 		暂无描述
SN74LVC74DR TI

获取价格

 		Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset 14-SOIC -40 to 85
SN74LVC74PWR TI

获取价格

 		8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT
SN74LVC821A TI

获取价格

 		10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821A_08 TI

获取价格

 		10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADB TI

获取价格

 		10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

与SN74LVC74AQPWRQ1相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证