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SN74LVC1G125-Q1_15 PDF预览

SN74LVC1G125-Q1_15

更新时间： 2024-11-21 02:58:51
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 102K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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SN74LVC1G125-Q1_15 数据手册

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SGES002A − APRIL 2003 − REVISED MAY 2004  
D
Qualification in Accordance With  
AEC-Q100  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
†
Operation  
D
Qualified for Automotive Applications  
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
DCK PACKAGE  
(TOP VIEW)  
Inputs Accept Voltages to 5.5 V  
Max t of 3.7 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
1
2
3
5
4
OE  
A
V
Y
CC  
CC  
GND  
†
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
This bus buffer gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is high.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
§
−40°C to 125°C SOT (SC-70) − DCK  
Reel of 2875  
1P1G125QDCKRQ1  
CM_  
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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