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SN74LVC1G125-Q1_V01 PDF预览

SN74LVC1G125-Q1_V01

更新时间： 2024-11-21 02:58:15
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德州仪器 - TI /
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SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output

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SN74LVC1G125-EP  
SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUT  
www.ti.com  
SCES455B–DECEMBER 2003–REVISED JUNE 2006  
FEATURES  
•
Controlled Baseline  
•
•
•
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
– One Assembly/Test Site, One Fabrication  
Site  
Ioff Supports Partial-Power-Down Mode  
Operation  
•
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.7 ns at 3.3 V  
– 1000-V Charged-Device Model (C101)  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
DCK PACKAGE  
(TOP VIEW)  
1
2
3
5
4
OE  
A
V
Y
CC  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
GND  
DESCRIPTION/ORDERING INFORMATION  
This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is high.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
CLVC1G125IDCKREP  
TOP-SIDE MARKING  
–40°C to 85°C  
–55°C to 125°C  
SOT (SC-70) – DCK  
SOT (SC-70) – DCK  
Reel of 3000  
Reel of 3000  
CMO  
CMO  
CLVC1G125MDCKREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
L
A
H
L
H
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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