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SN74LVC1G126DBV PDF预览

SN74LVC1G126DBV

更新时间: 2024-11-18 22:34:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 121K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74LVC1G126DBV 技术参数

生命周期:Obsolete包装说明:GREEN, PLASTIC, SOT-23, 5 PIN
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.57Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G5
长度:2.9 mm逻辑集成电路类型:BUS DRIVER
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH传播延迟(tpd):8 ns
座面最大高度:1.45 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
宽度:1.6 mmBase Number Matches:1

SN74LVC1G126DBV 数据手册

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SN74LVC1G126  
SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
SCES224C – APRIL 1999 – REVISED FEBRUARY 2000  
DBV OR DCK PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
I
Feature Supports Partial-Power-Down  
off  
OE  
A
GND  
V
Y
1
2
3
5
4
CC  
Mode Operation  
Supports 5-V V  
Operation  
CC  
Package Options Include Plastic  
Small-Outline Transistor (DBV, DCK)  
Packages  
description  
This single bus buffer gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G126 is a single bus driver/line driver with a 3-state output. The output is disabled when the  
output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
The SN74LVC1G126 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
logic symbol  
1
2
OE  
A
EN  
4
Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
logic diagram (positive logic)  
1
2
OE  
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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