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SCES527A − DECEMBER 2003 − REVISED MAY 2004
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
D
D
Low Power Consumption, 10-µA Max I
24-mA Output Drive at 3.3 V
CC
I
Supports Partial-Power-Down Mode
off
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
D
D
D
D
Enhanced Product-Change Notification
†
Qualification Pedigree
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Supports 5-V V
Operation
CC
Inputs Accept Voltages to 5.5 V
− 1000-V Charged-Device Model (C101)
Max t of 3.7 ns at 3.3 V
pd
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
V
Y
CC
description/ordering information
This single bus buffer gate is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
§
−40°C to 85°C
SOT (SC-70) − DCK Reel of 3000
CLVC1G126IDCKREP
CN_
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
DCK: The actual top-side marking has one additional character that designates the assembly/test site.
§
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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