5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74LVC1G126-EP
SN74LVC1G126-EP PDF预览

SN74LVC1G126-EP

更新时间： 2024-11-19 12:22:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 402K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

阅读下载

中文翻译

获取价格

SN74LVC1G126-EP 数据手册

 浏览型号SN74LVC1G126-EP的Datasheet PDF文件第2页浏览型号SN74LVC1G126-EP的Datasheet PDF文件第3页浏览型号SN74LVC1G126-EP的Datasheet PDF文件第4页浏览型号SN74LVC1G126-EP的Datasheet PDF文件第5页浏览型号SN74LVC1G126-EP的Datasheet PDF文件第6页浏览型号SN74LVC1G126-EP的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢈ ꢇꢉ ꢊꢋ ꢌꢍ  
ꢀꢎ ꢁꢈ ꢄ ꢌ ꢏꢐꢀ ꢏꢐꢑ ꢑ ꢌ ꢒ ꢈ ꢓꢔꢌ  
ꢕ ꢎꢔ ꢖ ꢗ ꢋꢀꢔꢓꢔ ꢌ ꢘ ꢐꢔ ꢍꢐ ꢔ  
SCES527A − DECEMBER 2003 − REVISED MAY 2004  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
D
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
CC  
I
Supports Partial-Power-Down Mode  
off  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
D
D
D
D
Enhanced Product-Change Notification  
†
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Supports 5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
− 1000-V Charged-Device Model (C101)  
Max t of 3.7 ns at 3.3 V  
pd  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
DCK PACKAGE  
(TOP VIEW)  
1
2
3
5
4
OE  
A
GND  
V
Y
CC  
description/ordering information  
This single bus buffer gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
§
−40°C to 85°C  
SOT (SC-70) − DCK Reel of 3000  
CLVC1G126IDCKREP  
CN_  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
§
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢍ
ꢍ
ꢒ
ꢘ
ꢩ
ꢙ
ꢤ
ꢐ
ꢆ
ꢢ
ꢔ
ꢣ
ꢎ
ꢝ
ꢘ
ꢛ
ꢁ
ꢜ
ꢙ
ꢓ
ꢔ
ꢓ
ꢚ
ꢛ
ꢥ
ꢜ
ꢝ
ꢣ
ꢞ
ꢟ
ꢠ
ꢠ
ꢡ
ꢡ
ꢚ
ꢚ
ꢝ
ꢝ
ꢛ
ꢛ
ꢚ
ꢢ
ꢢ
ꢦ
ꢣ
ꢤ
ꢞ
ꢞ
ꢥ
ꢥ
ꢛ
ꢡ
ꢠ
ꢟ
ꢢ
ꢢ
ꢝ
ꢜ
ꢦ
ꢔꢥ  
ꢤ
ꢧ
ꢢ
ꢨ
ꢚ
ꢣ
ꢠ
ꢢ
ꢡ
ꢚ
ꢡ
ꢝ
ꢞ
ꢛ
ꢤ
ꢩ
ꢠ
ꢛ
ꢡ
ꢡ
ꢥ
ꢢ
ꢪ
Copyright 2004, Texas Instruments Incorporated  
ꢞ
ꢝ
ꢣ
ꢡ
ꢝ
ꢞ
ꢟ
ꢡ
ꢝ
ꢢ
ꢦ
ꢚ
ꢜ
ꢚ
ꢣ
ꢥ
ꢞ
ꢡ
ꢫ
ꢡ
ꢥ
ꢞ
ꢝ
ꢜ
ꢬ
ꢠ
ꢎ
ꢛ
ꢟ
ꢥ
ꢢ
ꢡ
ꢠ
ꢛ
ꢩ
ꢠ
ꢞ
ꢩ
ꢭ
ꢠ
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢞ
ꢞ
ꢠ
ꢛ
ꢡ
ꢮ
ꢪ
ꢍ
ꢞ
ꢝ
ꢩ
ꢤ
ꢣ
ꢡ
ꢚ
ꢝ
ꢛ
ꢦ
ꢞ
ꢝ
ꢣ
ꢥ
ꢢ
ꢢ
ꢚ
ꢛ
ꢯ
ꢩ
ꢝ
ꢥ
ꢢ
ꢛ
ꢝ
ꢡ
ꢛ
ꢥ
ꢣ
ꢥ
ꢢ
ꢢ
ꢠ
ꢞ
ꢚ
ꢨ
ꢮ
ꢚ
ꢛ
ꢣ
ꢨ
ꢤ
ꢩ
ꢥ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

SN74LVC1G126-EP 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC1G126-Q1 TI

功能相似

 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

与SN74LVC1G126-EP相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC1G126-Q1 TI

获取价格

 		SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74LVC1G126-Q1_08 TI

获取价格

 		SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74LVC1G126-Q1_V01 TI

获取价格

 		SN74LVC1G126-Q1 Single Bus Buffer Gate With 3-State Output
SN74LVC1G126YEAR ROCHESTER

获取价格

 		LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PBGA5, MO-211EA, DSBGA-5
SN74LVC1G126YEPR TI

获取价格

 		LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PBGA5, DSBGA-5
SN74LVC1G126YEPR ROCHESTER

获取价格

 		LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PBGA5, DSBGA-5
SN74LVC1G126YZAR ROCHESTER

获取价格

 		LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PBGA5, GREEN, MO-211EA, DSBGA-5
SN74LVC1G126YZPR TI

获取价格

 		SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74LVC1G126YZPR ROCHESTER

获取价格

 		LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, BGA5, GREEN, DSBGA-5
SN74LVC1G132 TI

获取价格

 		SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

与SN74LVC1G126-EP相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证