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SN74AUC1G74DCUR

更新时间： 2024-09-08 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
12页 267K
描述
SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET

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中文翻译

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SN74AUC1G74DCUR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：VSSOP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.08Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：3365
Samacsys Pin Count：8Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：DCU (R-PDSO-G8)
Samacsys Released Date：2015-04-16 09:48:08Is Samacsys：N
系列：AUCJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：2.3 mm
负载电容（CL）：15 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：200000000 Hz最大I（ol）：0.009 A
湿度敏感等级：1位数：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装等效代码：TSSOP8,.12,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/2.5 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：3.8 ns
传播延迟（tpd）：3.8 ns认证状态：Not Qualified
座面最大高度：0.9 mm子类别：FF/Latches
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：2 mm最小 fmax：275 MHz
Base Number Matches：1

SN74AUC1G74DCUR 数据手册

 浏览型号SN74AUC1G74DCUR的Datasheet PDF文件第2页浏览型号SN74AUC1G74DCUR的Datasheet PDF文件第3页浏览型号SN74AUC1G74DCUR的Datasheet PDF文件第4页浏览型号SN74AUC1G74DCUR的Datasheet PDF文件第5页浏览型号SN74AUC1G74DCUR的Datasheet PDF文件第6页浏览型号SN74AUC1G74DCUR的Datasheet PDF文件第7页 
SN74AUC1G74  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES537A–DECEMBER 2003–REVISED AUGUST 2005  
FEATURES  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
•
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
Sub-1-V Operable  
– 1000-V Charged-Device Model (C101)  
Max tpd of 1.5 ns at 1.8 V  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
Q
CLR  
PRE  
GND  
Q
D
CLK  
CLK  
D
Q
GND  
V
CC  
1
2
3
4
8
7
6
5
1
2
8
7
CLK  
D
V
CC  
3 6  
PRE  
CLR  
Q
2
7
PRE  
1 8  
V
CC  
3
4
6
5
Q
CLR  
Q
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for  
higher frequencies, the CLR input overrides the PRE input when they are both low.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
Tape and reel  
Tape and reel  
SN74AUC1G74YEPR  
_ _ _UP_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AUC1G74YZPR  
–40°C to 85°C  
SSOP – DCT  
Tape and reel  
Tape and reel  
SN74AUC1G74DCTR  
SN74AUC1G74DCUR  
U74_ _ _  
UP_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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SN74AUC1G74DCUR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G74RSER TI

完全替代

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74AUC1G74DCTR TI

完全替代

 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET
SN74AUC1G74DCURE4 TI

完全替代

 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET

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