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SN74AUC1G74RSERG4

更新时间： 2024-11-24 05:17:43
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德州仪器 - TI 触发器
页数 文件大小 规格书
15页 606K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AUC1G74  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES537D–DECEMBER 2003–REVISED JUNE 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Low Power Consumption, 10-μA Max ICC  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 1.5 ns at 1.8 V  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
RSE PACKAGE  
(TOP VIEW)  
YZP OR YZT PACKAGE  
(BOTTOM VIEW)  
4
3
2
1
5
6
7
8
Q
GND  
Q
CLK  
D
VCC  
1
2
3
4
8
7
6
5
1
8
7
CLK  
D
VCC  
CLR  
PRE  
PRE  
CLR  
Q
D
CLK  
2
Q
PRE  
V
CC  
GND  
VCC  
8
4
GND  
3
4
6
5
Q
CLR  
Q
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for  
higher frequencies, the CLR input overrides the PRE input when they are both low.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74AUC1G74RSERG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G74RSER TI

完全替代

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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