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SN74AUC1G80YZAR PDF预览

SN74AUC1G80YZAR

更新时间： 2024-11-24 09:15:23
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
12页 312K
描述
SINGLE POSITIVE-EDGE-TRIGERED D-TYPE FLIP-FLOP

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中文翻译

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SN74AUC1G80YZAR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DSBGA包装说明：VFBGA, BGA5,2X3,20
针数：5Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.65系列：AUC
JESD-30 代码：R-XBGA-B5长度：1.4 mm
负载电容（CL）：15 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：200000000 Hz最大I（ol）：0.005 A
位数：1功能数量：1
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：UNSPECIFIED
封装代码：VFBGA封装等效代码：BGA5,2X3,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.2/2.5 VProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：3.9 ns认证状态：Not Qualified
座面最大高度：0.5 mm子类别：FF/Latches
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：0.9 mm
最小 fmax：275 MHzBase Number Matches：1

SN74AUC1G80YZAR 数据手册

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SCES388H − MARCH 2002 − REVISED FEBRUARY 2004  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1
2
3
5
4
D
CLK  
GND  
V
CC  
Q
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
YEA OR YZA PACKAGE  
(BOTTOM VIEW)  
D
D
D
D
D
Sub 1-V Operable  
Max t of 1.9 ns at 1.8 V  
pd  
Low Power Consumption, 10-µA Max I  
3 4  
2
GND  
CLK  
D
Q
CC  
8-mA Output Drive at 1.8 V  
1 5  
V
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V , but is designed  
CC  
specifically for 1.65-V to 1.95-V V  
operation.  
CC  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
‡
NanoStar  
WCSP (DSBGA) − YEA  
Tape and reel SN74AUC1G80YEAR  
_ _ _UX_  
NanoFree  
WCSP (DSBGA) − YZA (Pb-free)  
Tape and reel SN74AUC1G80YZAR  
−40°C to 85°C  
SOT (SOT-23) − DBV  
Tape and reel SN74AUC1G80DBVR  
Tape and reel SN74AUC1G80DCKR  
U80_  
UX_  
SOT (SC-70) − DCK  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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