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SN74AUC1GU04_10 PDF预览

SN74AUC1GU04_10

更新时间： 2024-11-02 11:47:39
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
12页 445K
描述
SINGLE INVERTER GATE

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SN74AUC1GU04_10 数据手册

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SN74AUC1GU04  
SINGLE INVERTER GATE  
www.ti.com  
SCES371L–SEPTEMBER 2001–REVISED APRIL 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
±8-mA Output Drive at 1.8 V  
Unbuffered Output  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
•
•
Sub-1-V Operable  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Max tpd of 2.4 ns at 1.8 V  
Low Power Consumption, 10-µA Max ICC  
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
4
5
Y
GND  
A
NC  
A
V
Y
1
2
3
5
1
2
3
6
5
4
CC  
NC  
A
VCC  
NC  
Y
1
2
3
5
NC  
A
V
CC  
2
1
DNU  
V
CC  
GND  
4
GND  
4
Y
GND  
DNU - Do not use  
NC – No internal connection  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC  
operation.  
The SN74AUC1GU04 contains one inverter with an unbuffered output and performs the Boolean function Y = A.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
ORDERING INFORMATION  
ORDERABLE PART  
TA  
PACKAGE(1)(2)  
NanoFree™ – WCSP  
TOP-SIDE MARKING(3)  
NUMBER  
(DSBGA)  
0.23-mm Large Bump – YZP  
(Pb-free)  
Reel of 3000  
SN74AUC1GU04YZPR  
_ _ _UD_  
–40°C to 85°C  
SON – DRY  
Reel of 5000  
Reel of 300  
Reel of 300  
SN74AUC1GU04DRYR  
SN74AUC1GU04DBVR  
SN74AUC1GU04DCKR  
PREVIEW  
UU4_  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
UD_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2001–2007, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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