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SN74AUC240RGYR PDF预览

SN74AUC240RGYR

更新时间: 2024-11-24 03:57:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
13页 464K
描述
OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

SN74AUC240RGYR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.59Is Samacsys:N
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:AUCJESD-30 代码:R-PQCC-N20
JESD-609代码:e4长度:4.5 mm
负载电容(CL):15 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.009 A湿度敏感等级:2
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC20/24,.14X.18,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法:TR
峰值回流温度(摄氏度):260电源:1.2/2.5 V
最大电源电流(ICC):0.02 mAProp。Delay @ Nom-Sup:3.3 ns
传播延迟(tpd):3.3 ns认证状态:Not Qualified
座面最大高度:1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:3.5 mmBase Number Matches:1

SN74AUC240RGYR 数据手册

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SCES430A − MARCH 2003 − REVISED MARCH 2003  
RGY PACKAGE  
(TOP VIEW)  
D
D
Optimized for 1.8-V Operation and is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
I
Supports Partial-Power-Down Mode  
off  
1
20  
Operation  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
D
D
D
D
D
Sub 1-V Operable  
Max t of 1.7 ns at 1.8 V  
pd  
Low Power Consumption, 20-µA Max I  
CC  
8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
10  
11  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This octal buffer/driver is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V V  
CC  
operation.  
CC  
The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address  
drivers, clock drivers, and bus-oriented receivers and transmitters.  
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C QFN − RGY Tape and reel  
SN74AUC240RGYR  
MS240  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AUC240RGYR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC240RGYRG4 TI

完全替代

OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUC244RGYR TI

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OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74AUC245ZQNR TI

类似代替

OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS

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