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SN74AUC1G80YEPR PDF预览

SN74AUC1G80YEPR

更新时间: 2024-11-24 13:02:23
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德州仪器 - TI 触发器
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12页 461K
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SN74AUC1G80YEPR 数据手册

 浏览型号SN74AUC1G80YEPR的Datasheet PDF文件第2页浏览型号SN74AUC1G80YEPR的Datasheet PDF文件第3页浏览型号SN74AUC1G80YEPR的Datasheet PDF文件第4页浏览型号SN74AUC1G80YEPR的Datasheet PDF文件第5页浏览型号SN74AUC1G80YEPR的Datasheet PDF文件第6页浏览型号SN74AUC1G80YEPR的Datasheet PDF文件第7页 
SN74AUC1G80  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES388KMARCH 2002REVISED JANUARY 2007  
FEATURES  
Available in the Texas Instruments  
NanoFree™ Package  
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
Ioff Supports Partial-Power-Down Mode  
Operation  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 1.9 ns at 1.8 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
Q
VCC  
GND  
CLK  
D
D
CLK  
GND  
1
2
3
5
1
2
3
5
D
CLK  
GND  
VCC  
5
VCC  
4
Q
4
Q
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP  
(Pb-free)  
Reel of 3000  
SN74AUC1G80YZPR  
_ _ _UX_  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
Reel of 3000  
Reel of 3000  
SN74AUC1G80DBVR  
SN74AUC1G80DCKR  
U80_  
UX_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2002–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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