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SN74AUC1G79_08 PDF预览

SN74AUC1G79_08

更新时间： 2024-11-24 05:17:43
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德州仪器 - TI 触发器
页数 文件大小 规格书
12页 473K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74AUC1G79_08 数据手册

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SN74AUC1G79  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES387K–MARCH 2002–REVISED APRIL 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 1.9 ns at 1.8 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
4
5
VCC  
Y
D
CLK  
GND  
1
2
3
5
1
2
3
6
5
4
GND  
B
D
CLK  
GND  
VCC  
NC  
Q
1
2
3
5
4
D
CLK  
GND  
VCC  
2
1
VCC  
A
4
Q
Q
See mechanical drawings for dimensions.  
NC – No internal connection  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
ORDERING INFORMATION  
ORDERABLE PART  
TA  
PACKAGE(1)(2)  
TOP-SIDE MARKING(3)  
NUMBER  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SON – DRY  
Reel of 3000  
SN74AUC1G79YZPR  
_ _ _UR_  
Reel of 5000  
Reel of 3000  
Reel of 3000  
SN74AUC1G79DRYR  
SN74AUC1G79DBVR  
SN74AUC1G79DCKR  
PREVIEW  
U79_  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
UR_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2002–2007, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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