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SN74AUC1G79DCKR PDF预览

SN74AUC1G79DCKR

更新时间： 2024-11-23 22:22:23
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 333K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74AUC1G79DCKR 数据手册

 浏览型号SN74AUC1G79DCKR的Datasheet PDF文件第2页浏览型号SN74AUC1G79DCKR的Datasheet PDF文件第3页浏览型号SN74AUC1G79DCKR的Datasheet PDF文件第4页浏览型号SN74AUC1G79DCKR的Datasheet PDF文件第5页浏览型号SN74AUC1G79DCKR的Datasheet PDF文件第6页浏览型号SN74AUC1G79DCKR的Datasheet PDF文件第7页 
SN74AUC1G79  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES387H–MARCH 2002–REVISED JUNE 2005  
FEATURES  
DBV OR DCK PACKAGE  
(TOP VIEW)  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
1
2
3
5
4
D
CLK  
GND  
V
CC  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Q
•
Ioff Supports Partial-Power-Down Mode  
Operation  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
•
•
•
•
•
Sub-1-V Operable  
Max tpd of 1.9 ns at 1.8 V  
3
2
1
4
5
GND  
CLK  
D
Q
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
V
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed  
specifically for 1.65-V to 1.95-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting  
the levels at the outputs.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™  
WCSP (DSBGA) – YEA  
SN74AUC1G79YEAR  
NanoFree™  
WCSP (DSBGA) – YZA (Pb-free)  
SN74AUC1G79YZAR  
SN74AUC1G79YEPR  
SN74AUC1G79YZPR  
Tape and reel  
_ _ _UR_  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
–40°C to 85°C  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
Tape and reel  
Tape and reel  
SN74AUC1G79DBVR  
SN74AUC1G79DCKR  
U79_  
UR_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2002–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74AUC1G79DCKR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G79DCKRE4 TI

类似代替

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUC1G79DCKRG4 TI

类似代替

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74AUP1G79DCKR TI

类似代替

 LOW POWER SINGLE POSITIVE EDGE TRIGGERRED D TYPE FLIP FLOP

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