5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> SN74ABTH16823DGG
SN74ABTH16823DGG PDF预览

SN74ABTH16823DGG

更新时间： 2024-11-24 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
9页 136K
描述
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74ABTH16823DGG 数据手册

 浏览型号SN74ABTH16823DGG的Datasheet PDF文件第2页浏览型号SN74ABTH16823DGG的Datasheet PDF文件第3页浏览型号SN74ABTH16823DGG的Datasheet PDF文件第4页浏览型号SN74ABTH16823DGG的Datasheet PDF文件第5页浏览型号SN74ABTH16823DGG的Datasheet PDF文件第6页浏览型号SN74ABTH16823DGG的Datasheet PDF文件第7页 
SN54ABTH16823, SN74ABTH16823  
18-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS664B – APRIL 1996 – REVISED MAY 1997  
SN54ABTH16823 . . . WD PACKAGE  
SN74ABTH16823 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1CLR  
1OE  
1Q1  
GND  
1Q2  
1Q3  
1CLK  
1CLKEN  
1D1  
GND  
1D2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
3
4
5
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
1D3  
6
at V  
= 5 V, T = 25°C  
CC  
A
V
V
7
CC  
CC  
High-Impedance State During Power Up  
and Power Down  
1Q4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
1Q9  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D4  
1D5  
1D6  
GND  
1D7  
1D8  
1D9  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
8
9
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Flow-Through Architecture Optimizes PCB  
Layout  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
OH  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2OE  
2CLR  
2D7  
2D8  
GND  
2D9  
2CLKEN  
2CLK  
description  
These 18-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
The ’ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input  
low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the  
clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently  
of the clock.  
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without need for interface or pullup components.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与SN74ABTH16823DGG相关器件

型号 品牌 获取价格 描述 数据表
SN74ABTH16823DGGR TI

获取价格

 		暂无描述
SN74ABTH16823DL TI

获取价格

 		18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABTH16823DLR TI

获取价格

 		暂无描述
SN74ABTH182502A TI

获取价格

 		SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182502AHV TI

获取价格

 		ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68
SN74ABTH182502APM TI

获取价格

 		SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182502APMLE TI

获取价格

 		ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64
SN74ABTH182504A TI

获取价格

 		SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182504APM TI

获取价格

 		SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182646A TI

获取价格

 		SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

与SN74ABTH16823DGG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证