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SN74ABTH182652APM PDF预览

SN74ABTH182652APM

更新时间： 2024-02-03 19:19:39
品牌 Logo 应用领域
德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
37页 574K
描述
SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS

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中文翻译

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SN74ABTH182652APM 技术参数

生命周期：Obsolete包装说明：LFQFP,
Reach Compliance Code：unknown风险等级：5.73
其他特性：SCANNABLE; A-PORT WITHOUT SERIES RESISTOR系列：ABT
JESD-30 代码：S-PQFP-G64长度：10 mm
负载电容（CL）：50 pF逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER
位数：9功能数量：2
端口数量：2端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
最大电源电流（ICC）：27 mA传播延迟（tpd）：8.4 ns
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：10 mm
Base Number Matches：1

SN74ABTH182652APM 数据手册

 浏览型号SN74ABTH182652APM的Datasheet PDF文件第2页浏览型号SN74ABTH182652APM的Datasheet PDF文件第3页浏览型号SN74ABTH182652APM的Datasheet PDF文件第4页浏览型号SN74ABTH182652APM的Datasheet PDF文件第5页浏览型号SN74ABTH182652APM的Datasheet PDF文件第6页浏览型号SN74ABTH182652APM的Datasheet PDF文件第7页 
SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A  
SCAN TEST DEVICES WITH  
18-BIT BUS TRANSCEIVERS AND REGISTERS  
SCBS167D – AUGUST 1993 – REVISED JULY 1996  
Members of the Texas Instruments  
One Boundary-Scan Cell Per I/O  
SCOPE Family of Testability Products  
Architecture Improves Scan Efficiency  
Members of the Texas Instruments  
Widebus Family  
SCOPE Instruction Set  
– IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
Include D-Type Flip-Flops and Control  
Circuitry to Provide Multiplexed  
Transmission of Stored and Real-Time Data  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
– Even-Parity Opcodes  
B-Port Outputs of ’ABTH182652A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
SN54ABTH18652A, SN54ABTH182652A . . . HV PACKAGE  
(TOP VIEW)  
9
8
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2
1 68 67 66 65 64 63 62 61  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
1A9  
NC  
10  
11  
12  
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18  
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25  
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60  
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51  
50  
49  
48  
47  
46  
45  
44  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
1B9  
V
CC  
NC  
V
2B1  
2B2  
2B3  
2B4  
GND  
2B5  
2B6  
2B7  
CC  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...37

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