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SMUN5115DW1T1G PDF预览

SMUN5115DW1T1G

更新时间： 2024-11-22 11:01:35
品牌 Logo 应用领域
安森美 - ONSEMI PC开关光电二极管小信号双极晶体管
页数 文件大小 规格书
20页 148K
描述
10kΩ, ∞ kΩ Dual PNP Bias Resistor Transistors (BRT)

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中文翻译

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SMUN5115DW1T1G 技术参数

是否无铅：不含铅生命周期：Active
包装说明：SMALL OUTLINE, R-PDSO-G6针数：6
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：1.58Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：227131
Samacsys Pin Count：6Samacsys Part Category：Integrated Circuit
Samacsys Package Category：SOT23 (6-Pin)Samacsys Footprint Name：SC-88 SC70-6 SOT-363 CASE 719B-02 ISSUE W
Samacsys Released Date：2015-09-14 02:41:33Is Samacsys：N
其他特性：BUILT IN BIAS RESISTOR最大集电极电流 (IC)：0.1 A
集电极-发射极最大电压：50 V配置：SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
最小直流电流增益 (hFE)：160JESD-30 代码：R-PDSO-G6
JESD-609代码：e3湿度敏感等级：1
元件数量：2端子数量：6
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：PNP最大功率耗散 (Abs)：0.385 W
参考标准：AEC-Q101子类别：BIP General Purpose Small Signal
表面贴装：YES端子面层：Tin (Sn)
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

SMUN5115DW1T1G 数据手册

 浏览型号SMUN5115DW1T1G的Datasheet PDF文件第2页浏览型号SMUN5115DW1T1G的Datasheet PDF文件第3页浏览型号SMUN5115DW1T1G的Datasheet PDF文件第4页浏览型号SMUN5115DW1T1G的Datasheet PDF文件第5页浏览型号SMUN5115DW1T1G的Datasheet PDF文件第6页浏览型号SMUN5115DW1T1G的Datasheet PDF文件第7页 
MUN5111DW1T1 Series  
Preferred Devices  
Dual Bias Resistor  
Transistors  
PNP Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
http://onsemi.com  
The BRT (Bias Resistor Transistor) contains a single transistor with a  
monolithic bias network consisting of two resistors; a series base resistor  
and a base−emitter resistor. These digital transistors are designed to  
replace a single device and its external resistor bias network. The BRT  
eliminates these individual components by integrating them into a single  
device. In the MUN5111DW1T1 series, two BRT devices are housed in  
the SOT−363 package which is ideal for low−power surface mount  
applications where board space is at a premium.  
(3)  
(2)  
(1)  
R
1
R
2
Q
1
Q
2
R
2
R
1
Features  
(4)  
(5)  
(6)  
• Simplifies Circuit Design  
• Reduces Board Space  
• Reduces Component Count  
• Pb−Free Packages are Available  
1
MAXIMUM RATINGS  
(T = 25°C unless otherwise noted, common for Q and Q )  
A
1
2
SOT−363  
CASE 419B  
STYLE 1  
Rating  
Symbol  
Value  
−50  
−50  
−100  
Unit  
Vdc  
Collector-Base Voltage  
V
CBO  
Collector-Emitter Voltage  
Collector Current  
V
Vdc  
CEO  
I
mAdc  
C
THERMAL CHARACTERISTICS  
MARKING DIAGRAM  
Characteristic  
(One Junction Heated)  
Symbol  
Max  
Unit  
6
Total Device Dissipation  
T = 25°C  
A
P
187 (Note 1)  
256 (Note 2)  
mW  
D
xx M G  
1.5 (Note 1) mW/°C  
2.0 (Note 2)  
Derate above 25°C  
G
1
Thermal Resistance,  
Junction-to-Ambient  
R
q
JA  
670 (Note 1) °C/W  
490 (Note 2)  
Characteristic  
(Both Junctions Heated)  
xx = Device Code (Refer to page 2)  
Symbol  
Max  
Unit  
M
= Date Code  
Total Device Dissipation  
P
250 (Note 1)  
385 (Note 2)  
2.0 (Note 1) mW/°C  
3.0 (Note 2)  
mW  
D
G
= Pb−Free Package  
T = 25°C  
A
(Note: Microdot may be in either location)  
Derate above 25°C  
ORDERING INFORMATION  
See detailed ordering and shipping information in the table on  
page 2 of this data sheet.  
Thermal Resistance,  
Junction-to-Ambient  
R
q
JA  
493 (Note 1) °C/W  
325 (Note 2)  
Thermal Resistance,  
Junction-to-Lead  
R
q
JL  
188 (Note 1) °C/W  
208 (Note 2)  
DEVICE MARKING INFORMATION  
Junction and Storage Temperature Range T , T  
−55 to +150  
°C  
See specific marking information in the device marking table  
on page 2 of this data sheet.  
J
stg  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
Preferred devices are recommended choices for future use  
and best overall value.  
1. FR−4 @ Minimum Pad  
2. FR−4 @ 1.0 x 1.0 inch Pad  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
September, 2005 − Rev. 6  
MUN5111DW1T1/D  
 
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与SMUN5115DW1T1G相关器件

型号 品牌 获取价格 描述 数据表
SMUN5115T1G ONSEMI

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 		Digital Transistors (BRT) R1 = 10 k, R2 =  k
SMUN5116DW1T1G ONSEMI

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 		Dual PNP Bias Resistor Transistors R1 = 4.7 kOhm, R2 =  kOhm
SMUN5131DW1T1G ONSEMI

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 		Dual PNP Bias Resistor Transistors R1 = 2.2 k, R2 = 2.2 k
SMUN5133T1G ONSEMI

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 		Digital Transistors (BRT) R1 = 4.7 k, R2 = 47 k
SMUN5211DW SECOS

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 		NPN Multi-Chip Built-in Resistors Transistor
SMUN5211DW1T1G ONSEMI

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 		Dual NPN Bias Resistor Transistors
SMUN5211T1G ONSEMI

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 		Digital Transistors (BRT) R1 = 10 k, R2 = 10 k
SMUN5211T3G ONSEMI

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 		Digital Transistors (BRT) R1 = 10 k, R2 = 10 k
SMUN5212DW SECOS

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 		NPN Multi-Chip Built-in Resistors Transistor
SMUN5212T1G ONSEMI

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 		Digital Transistors (BRT) R1 = 22 k, R2 = 22 k

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