Datasheet > SiRA74DP

SiRA74DP

更新时间： 2024-11-22 14:50:59

品牌	Logo	应用领域
威世 - VISHAY		/
页数	文件大小	规格书
9页	261K
描述
N-Channel 40 V (D-S) 150 °C MOSFET

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SiRA74DP 数据手册

SiRA74DP

Vishay Siliconix

www.vishay.com

N-Channel 40 V (D-S) 150 °C MOSFET

FEATURES

PowerPAK^®SO-8 Single

• TrenchFET^®Gen IV power MOSFET

• Tuned for the lowest R_DS-Q_ossFOM

• 100 % R_gand UIS tested

• Q_gd/Q_gsratio < 1 optimizes switching characteristics

• Optimized for wave soldering

• Flexible leads increase resilience to board flexing

• Material categorization: for definitions of compliance

please see www.vishay.com/doc?99912

Top View

Bottom View

APPLICATIONS

PRODUCT SUMMARY

V_DS(V)

R_DS(on)max. () at V_GS= 10 V

• Synchronous rectification

• High power density DC/DC

0.0042

0.0061

12.4

• DC/AC inverters

_DS(on)max. () at V_GS= 4.5 V

Q_gtyp. (nC)

_D(A) ^a

Configuration

• Switch mode power supplies

81.2

Single

N-Channel MOSFET

ORDERING INFORMATION

Package

PowerPAK SO-8

Lead (Pb)-free and halogen-free

SiRA74DP-T1-GE3

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C, unless otherwise noted)

PARAMETER

SYMBOL

LIMIT

+20 / -16

81.2

64.2

24 ^b

19.2 ^b

150

3.7 ^{b, c}

UNIT

Drain-source voltage

Gate-source voltage

V_DS

V_GS

T_C= 25 °C

T_C= 70 °C

T_A= 25 °C

T_A= 70 °C

Continuous drain current (T_J= 150 °C)

I_D

Pulsed drain current (t = 100 μs)

I_DM

I_S

T_C= 25 °C

T_A= 25 °C

Continuous source-drain diode current

Single pulse avalanche current

Single pulse avalanche energy

I_AS

E_AS

46.2

29.6

L = 0.1 mH

T_C= 25 °C

T_C= 70 °C

T_A= 25 °C

T_A=70 °C

Maximum power dissipation

P_D

4.1 ^b

2.6 ^b

-55 to +150

260

Operating junction and storage temperature range

Soldering recommendations (peak temperature) ^c

T_J, T_stg

°C

THERMAL RESISTANCE RATINGS

PARAMETER

Maximum junction-to-ambient ^b

SYMBOL

R_thJA

R_thJC

TYPICAL

MAXIMUM

UNIT

t < 10 s

Steady state

2.7

°C/W

Maximum junction-to-case (drain)

2.1

Notes

a. T_C= 25 °C

b. Surface mounted on 1" x 1" FR4 board

c. t = 10 s

d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper

(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not

required to ensure adequate bottom side solder interconnection

e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components

f. Maximum under steady state conditions is 75 °C/W

S20-0500-Rev. A, 29-Jun-2020

Document Number: 77640

For technical questions, contact: pmostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

12 3 4 5 6 7...9

中文翻译

下载PDF

与SiRA74DP相关器件

型号	品牌	获取价格	描述	数据表
SiRA80DP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SiRA84BDP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SiRA84DP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SiRA88BDP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SiRA88DP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SIRA88DP-T1-GE3	VISHAY	获取价格	Power Field-Effect Transistor,
SiRA90DP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SiRA96DP	VISHAY	获取价格	N-Channel 30 V (D-S) MOSFET
SiRA99DP	VISHAY	获取价格	P-Channel 30 V (D-S) MOSFET
SiRB40DP	VISHAY	获取价格	Dual N-Channel 40 V (D-S) MOSFET

与SiRA74DP相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

27
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

19
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

49
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

47

产品中心

服务支持

精选活动

关于我们

帮助中心

SiRA74DP

SiRA74DP 数据手册

与SiRA74DP相关器件

与SiRA74DP相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SiRA74DP

SiRA74DP 数据手册

与SiRA74DP相关器件

与SiRA74DP相关文章

您还可以找

您在本页遇到什么问题？