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SI6933DQ PDF预览

SI6933DQ

更新时间: 2024-11-25 06:11:35
品牌 Logo 应用领域
威世 - VISHAY 晶体晶体管开关光电二极管
页数 文件大小 规格书
3页 212K
描述
Dual P-Channel Enhancement-Mode MOSFET

SI6933DQ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:compliant
风险等级:5.91Is Samacsys:N
最大漏极电流 (Abs) (ID):3.5 AFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-609代码:e0工作模式:ENHANCEMENT MODE
最高工作温度:150 °C极性/信道类型:P-CHANNEL
最大功率耗散 (Abs):1 W子类别:Other Transistors
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
Base Number Matches:1

SI6933DQ 数据手册

 浏览型号SI6933DQ的Datasheet PDF文件第2页浏览型号SI6933DQ的Datasheet PDF文件第3页 
SPICE Device Model Si6933DQ  
Vishay Siliconix  
Dual P-Channel Enhancement-Mode MOSFET  
CHARACTERISTICS  
P-Channel Vertical DMOS  
Macro Model (Subcircuit Model)  
Level 3 MOS  
Apply for both Linear and Switching Application  
Accurate over the 55 to 125°C Temperature Range  
Model the Gate Charge, Transient, and Diode Reverse Recovery  
Characteristics  
DESCRIPTION  
The attached spice model describes the typical electrical  
characteristics of the p-channel vertical DMOS. The subcircuit  
A novel gate-to-drain feedback capacitance network is used to model  
the gate charge characteristics while avoiding convergence difficulties  
of the switched Cgd model. All model parameter values are optimized  
to provide a best fit to the measured electrical data and are not  
intended as an exact physical interpretation of the device.  
mode  
is extracted and optimized over the 55 to 125°C  
temperature ranges under the pulsed 0-to-10V gate drive. The  
saturated output impedance is best fit at the gate bias near the  
threshold voltage.  
SUBCIRCUIT MODEL SCHEMATIC  
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate  
data sheet of the same number for guaranteed specification limits.  
Document Number: 71734  
12-Oct-01  
www.vishay.com  
1

SI6933DQ 替代型号

型号 品牌 替代类型 描述 数据表
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