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Si5936DU PDF预览

Si5936DU

更新时间: 2024-11-07 14:49:47
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威世 - VISHAY /
页数 文件大小 规格书
9页 188K
描述
Dual N-Channel 30 V (D-S) MOSFET

Si5936DU 数据手册

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Si5936DU  
Vishay Siliconix  
www.vishay.com  
Dual N-Channel 30 V (D-S) MOSFET  
FEATURES  
• TrenchFET® power MOSFET  
PowerPAK® ChipFET® Dual  
D1  
• Thermally enhanced PowerPAK® ChipFET®  
package  
- Small footprint area  
- Low on-resistance  
- Thin 0.8 mm profile  
• 100 % Rg tested  
• Material categorization: for definitions of compliance  
please see www.vishay.com/doc?99912  
D1  
7
8
D2  
6
D2  
5
1
S1  
2
G1  
3
4
G2  
S
2  
1
Top View  
Bottom View  
APPLICATIONS  
• Network  
Marking code: CF  
• System power DC/DC  
PRODUCT SUMMARY  
D
1
D
2
VDS (V)  
30  
0.030  
0.040  
3.5  
R
DS(on) max. () at VGS = 10 V  
DS(on) max. () at VGS = 4.5 V  
R
G
1
G
2
Qg typ. (nC)  
D (A) a  
Configuration  
I
6
S
1
S
2
Dual  
N-Channel MOSFET  
N-Channel MOSFET  
ORDERING INFORMATION  
Package  
Lead (Pb)-free and halogen-free  
PowerPAK ChipFET  
Si5936DU-T1-GE3  
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)  
PARAMETER  
SYMBOL  
LIMIT  
30  
UNIT  
Drain-source voltage  
Gate-source voltage  
VDS  
VGS  
V
20  
TC = 25 °C  
TC = 70 °C  
TA = 25 °C  
TA = 70 °C  
6 a  
6 a  
Continuous drain current (TJ = 150 °C)  
ID  
6 a, b, c  
5.3 b, c  
25  
A
Pulsed drain current (t = 300 μs)  
IDM  
IS  
TC = 25 °C  
6 a  
1.9 b, c  
10.4  
Continuous source-drain diode current  
TA = 25 °C  
TC = 25 °C  
T
C = 70 °C  
6.7  
Maximum power dissipation  
PD  
W
TA = 25 °C  
TA = 70 °C  
2.3 b, c  
1.5 b, c  
-55 to +150  
260  
Operating junction and storage temperature range  
Soldering recommendations (peak temperature) d, e  
TJ, Tstg  
°C  
THERMAL RESISTANCE RATINGS  
PARAMETER  
Maximum junction-to-ambient b, f  
Maximum junction-to-case (drain)  
SYMBOL  
TYPICAL  
43  
MAXIMUM  
UNIT  
t 5 s  
Steady state  
RthJA  
RthJC  
55  
12  
°C/W  
9.5  
Notes  
a. Package limited  
b. Surface mounted on 1" x 1" FR4 board  
c. t = 5 s  
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed  
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed  
and is not required to ensure adequate bottom side solder interconnection  
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components  
f. Maximum under steady state conditions is 105 °C/W  
S12-2729-Rev. A, 12-Nov-12  
Document Number: 62804  
1
For technical questions, contact: pmostechsupport@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  

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