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Si5948DU PDF预览

Si5948DU

更新时间: 2024-11-07 14:53:43
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威世 - VISHAY /
页数 文件大小 规格书
9页 386K
描述
Dual N-Channel 40 V (D-S) MOSFET

Si5948DU 数据手册

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Si5948DU  
Vishay Siliconix  
www.vishay.com  
Dual N-Channel 40 V (D-S) MOSFET  
FEATURES  
• TrenchFET® power MOSFET  
PRODUCT SUMMARY  
VDS (V)  
RDS(on) () MAX.  
0.082 at VGS = 10 V  
0.094 at VGS = 4.5 V  
ID (A)  
6 a  
6 a  
Qg (TYP.)  
• 100 % Rg and UIS tested  
40  
2.2 nC  
• New thermally enhanced PowerPAK®  
ChipFET® package  
- Small footprint area  
- Low on-resistance  
- Thin 0.8 mm profile  
PowerPAK® ChipFET® Dual  
D1  
8
• Material categorization: for definitions of compliance  
please see www.vishay.com/doc?99912  
D1  
7
D2  
6
D2  
5
APPLICATIONS  
• DC/DC power supply  
1
S1  
2
G1  
3
S
2  
D
1
D
2
4
G2  
1
Top View  
Bottom View  
G
G
2
1
Marking Code: CG  
Ordering Information:  
Si5948DU-T1-GE3 (lead (Pb)-free and halogen-free)  
N-Channel MOSFET  
N-Channel MOSFET  
S
1
S
2
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)  
PARAMETER  
Drain-Source Voltage  
Gate-Source Voltage  
SYMBOL  
VDS  
LIMIT  
40  
UNIT  
V
VGS  
20  
TC = 25 °C  
6 a  
TC = 70 °C  
TA = 25 °C  
TA = 70 °C  
5.5  
Continuous Drain Current (TJ = 150 °C)  
ID  
3.7 b, c  
2.9 b, c  
10  
A
Pulsed Drain Current (t = 100 μs)  
IDM  
IS  
TC = 25 °C  
5.8  
1.7 b, c  
Continuous Source-Drain Diode Current  
TA = 25 °C  
Single Pulse Avalanche Current  
Avalanche Energy  
IAS  
6
L = 0.1 mH  
EAS  
1.8  
mJ  
W
TC = 25 °C  
7
TC = 70 °C  
TA = 25 °C  
TA = 70 °C  
4.4  
Maximum Power Dissipation  
PD  
2 b, c  
1.3 b, c  
-55 to +150  
260  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature) d, e  
TJ, Tstg  
°C  
THERMAL RESISTANCE RATINGS  
PARAMETER  
Maximum Junction-to-Ambient b, f  
SYMBOL  
RthJA  
TYPICAL  
MAXIMUM  
UNIT  
t 5 s  
Steady State  
52  
15  
62  
18  
°C/W  
Maximum Junction-to-Case (Drain)  
RthJC  
Notes  
a. Package limited.  
b. Surface mounted on 1" x 1" FR4 board.  
c. t = 5 s.  
d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed  
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed  
and is not required to ensure adequate bottom side solder interconnection.  
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.  
f. Maximum under steady state conditions is 105 °C/W.  
S16-1127-Rev. A, 06-Jun-16  
Document Number: 76424  
1
For technical questions, contact: pmostechsupport@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  

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