Order this document
by MCM6323A/D
SEMICONDUCTOR TECHNICAL DATA
MCM6323A
Product Preview
64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
YJ PACKAGE
400 MIL SOJ
CASE 919–01
TS PACKAGE
44–LEAD
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB and UB) allow individual bytes to be
written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack-
age and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
TSOP TYPE II
CASE 924A–01
PIN ASSIGNMENT
A
A
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
A
•
•
•
•
•
•
•
•
Single 3.3 V ± 0.3 V Power Supply
Fast Access Time: 10, 12, 15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
A
A
A
A
G
A
UB
LB
E
Fully Static Operation
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
Power Operation: 140/135/130 mA Maximum, Active AC
Industrial Temperature Option: – 40 to + 85°C
Part Number: SCM6323AYJ10A
V
11
12
13
14
15
16
17
34
33
32
31
30
29
28
V
BLOCK DIAGRAM
DD
SS
V
V
SS
DD
OUTPUT
ENABLE
BUFFER
G
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
DQa
DQa
DQa
DQa
W
DQb
DQb
DQb
DQb
NC
A
HIGH
BYTE
OUTPUT
BUFFER
7
8
DQb
8
8
A
ADDRESS
BUFFERS
9
ROW
COLUMN
16
DECODER DECODER
A
18
19
20
21
22
27
26
25
24
23
HIGH
BYTE
WRITE
DRIVER
A
A
8
8
A
A
CHIP
E
ENABLE
BUFFER
A
A
NC
NC
SENSE
AMPS
64K x 16
BIT
16
LOW
BYTE
OUTPUT
BUFFER
WRITE
ENABLE
BUFFER
MEMORY
ARRAY
W
8
8
DQa
8
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte
DQa . . . . . . . . . . . . Lower Data Input/Output
DQb . . . . . . . . . . . . Upper Data Input/Output
LOW
BYTE
WRITE
DRIVER
8
8
LB
UB
BYTE
ENABLE
BUFFER
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
V
DD
V
SS
. . . . . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
REV 1
10/17/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM6323A
1