Datasheet > SCM63P733ATQ133

SCM63P733ATQ133

更新时间： 2024-11-10 20:02:47

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器内存集成电路
页数	文件大小	规格书
17页	147K
描述
128KX32 CACHE SRAM, 4ns, PQFP100, TQFP-100

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技术参数
数据手册

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SCM63P733ATQ133 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.7	最长访问时间：	4 ns
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	4194304 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
功能数量：	1	端子数量：	100
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	128KX32
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

SCM63P733ATQ133 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63P733A/D

MCM63P733A

SCM63P733A

128K x 32 Bit Pipelined

BurstRAM Synchronous

Fast Static RAM

The MCM63P733A and SCM63P733A are 4M–bit synchronous fast static

RAMs designed to provide a burstable, high performance, secondary cache.

The MCM63P733A and SCM63P733A (organized as 128K words by 32 bits)

are fabricated in Motorola’s high performance silicon gate CMOS technology.

These devices integrate input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced

parts count in cache data RAM applications. Synchronous design allows

precise cycle control with the use of an external clock (K). CMOS circuitry re-

duces the overall power consumption of the integrated functions for greater

reliability.

TQ PACKAGE

TQFP

CASE 983A–01

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63P733A and SCM63P733A

(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate

of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

TheMCM63P733AandSCM63P733Aoperatefroma3.3Vcorepowersupply

and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs

are JEDEC standard JESD8–5 compatible.

•

MCM63P733A–150 = 3.8 ns Access/6.7 ns Cycle (150 MHz)

MCM63P733A/SCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz)

MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz)

MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz)

3.3 V +10%,–5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

Single–Cycle Deselect

Sleep Mode (ZZ)

–40° to 85°C Extended Operating Temperatures (SCM63P733A only)

100–Pin TQFP Package

•

REV 5

9/21/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM63P733A•SCM63P733A

12 3 4 5 6 7...17

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与SCM63P733ATQ133相关器件

型号	品牌	获取价格	描述	数据表
SCM63P733ATQ133R	MOTOROLA	获取价格	Cache SRAM, 128KX32, 4ns, CMOS, PQFP100, TQFP-100
SCM63P733ATQ133R	NXP	获取价格	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC
SCM6926WJ10C	MOTOROLA	获取价格	128KX8 STANDARD SRAM, 10ns, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6926WJ10RC	MOTOROLA	获取价格	128KX8 STANDARD SRAM, 10ns, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6926WJ12C	MOTOROLA	获取价格	128KX8 STANDARD SRAM, 12ns, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6926WJ15C	MOTOROLA	获取价格	Standard SRAM, 128KX8, 15ns, BICMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6926WJ15RC	MOTOROLA	获取价格	Standard SRAM, 128KX8, 15ns, BICMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6926WJ8RC	MOTOROLA	获取价格	Standard SRAM, 128KX8, 8ns, BICMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6929WJ10C	MOTOROLA	获取价格	256KX4 STANDARD SRAM, 10ns, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
SCM6929WJ15RC	MOTOROLA	获取价格	256KX4 STANDARD SRAM, 15ns, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

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