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SCM6341ZP12AR PDF预览

SCM6341ZP12AR

更新时间: 2024-11-10 12:59:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
10页 128K
描述
128KX24 STANDARD SRAM, 12ns, PBGA119, PLASTIC, BGA-119

SCM6341ZP12AR 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.77
最长访问时间:12 nsJESD-30 代码:R-PBGA-B119
长度:22 mm内存密度:3145728 bit
内存集成电路类型:STANDARD SRAM内存宽度:24
功能数量:1端口数量:1
端子数量:119字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX24输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:2.4 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:14 mm
Base Number Matches:1

SCM6341ZP12AR 数据手册

 浏览型号SCM6341ZP12AR的Datasheet PDF文件第2页浏览型号SCM6341ZP12AR的Datasheet PDF文件第3页浏览型号SCM6341ZP12AR的Datasheet PDF文件第4页浏览型号SCM6341ZP12AR的Datasheet PDF文件第5页浏览型号SCM6341ZP12AR的Datasheet PDF文件第6页浏览型号SCM6341ZP12AR的Datasheet PDF文件第7页 
Order this document  
by MCM6341/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6341  
Advance Information  
128K x 24 Bit Static Random  
Access Memory  
The MCM6341 is a 3,145,728–bit static random access memory organized as  
131,072 words of 24 bits. Static design eliminates the need for external clocks  
or timing strobes.  
The MCM6341 is equipped with chip enable (E1, E2, E3) and output enable  
(G) pins, allowing for greater system flexibility and eliminating bus contention  
problems.  
ZP PACKAGE  
PBGA  
CASE 999–02  
The MCM6341 is available in a 119–bump PBGA package.  
PIN NAMES  
Single 3.3 V ± 10% Power Supply  
A . . . . . . . . . . . . . . . . . . . . . . Address Inputs  
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . . . Output Enable  
E1, E2, E3 . . . . . . . . . . . . . . . . Chip Enable  
DQ . . . . . . . . . . . . . . . . . Data Input/Output  
NC . . . . . . . . . . . . . . . . . . . . No Connection  
Fast Access Time: 10/11/12/15 ns  
Equal Address and Chip Enable Access Time  
All Inputs and Outputs are TTL Compatible  
Three–State Outputs  
Power Operation: 280/275/270/260 mA Maximum, Active AC  
Commercial Temperature (0°C to 70°C) and  
Industrial Temperature (– 40°C to + 85°C) Options  
V
DD  
V
SS  
. . . . . . . . . . . . . + 3.3 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . Ground  
BLOCK DIAGRAM  
A
A
A
A
A
A
A
A
A
ROW  
DECODER  
MEMORY MATRIX  
COLUMN I/O  
COLUMN DECODER  
DQ  
DQ  
INPUT  
DATA  
CONTROL  
A
A
A
A
A
A
A
A
DQ  
DQ  
E1  
E2  
E3  
W
G
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 2  
2/18/98  
Motorola, Inc. 1998  

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