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S1M0W026B0J1 PDF预览

S1M0W026B0J1

更新时间: 2024-02-25 08:59:03
品牌 Logo 应用领域
精工 - SEIKO 静态存储器内存集成电路
页数 文件大小 规格书
12页 131K
描述
128KX16 STANDARD SRAM, 100ns, PBGA48, TFBGA-48

S1M0W026B0J1 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA,针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:100 nsJESD-30 代码:R-PBGA-B48
长度:8 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:48
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX16
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):2.2 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:7 mmBase Number Matches:1

S1M0W026B0J1 数据手册

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PF988-10  
S1M0W026B0J1/7  
2M-bit Static RAM  
Super Low Voltage Operation and Low Current Consumption  
Access Time 100ns (1.8V) / 70ns (2.2V)  
131,072 Words x 16-bit Asynchronous  
Wide Temperature Range  
DESCRIPTION  
The S1M0W026B0J1/7 is a 131,072 words x 16-bit asynchronous, random access memory on a monolithic  
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage  
with back-up batteries. The asynchronous and static nature of the memory requires no external clock and no  
refreshing circuit. It is possible to contorol the data width by the data byte control. 3-state output allows easy  
expansion of memory capacity. The temperature range of the S1M0W026B0J1/7 is from –40 to 85°C, and it is  
suitable for the industrial products.  
FEATURES  
Fast Access time ........................ 100ns (at 1.8V) / 70ns (at 2.2V)  
Low supply current ..................... LL Version  
Completely static........................ No clock required  
Supply voltage............................ 1.8V to 3.0V  
3-state output with wired-OR capability  
Non-volatile storage with back-up batteries  
Package ..................................... S1M0W026B0J  
TFBGA-48 pin (Tape CSP)  
BLOCK DIAGRAM  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
9
8
512  
Memory Cell Array  
512 x 256 x 16  
256x16  
256  
Column Gate  
CS  
16  
LB  
UB  
OE  
WE  
I/O Buffer  
I/O1  
I/O16  
Rev.1.4  
Rev.1.4  

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