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S1M0W045B0J3 PDF预览

S1M0W045B0J3

更新时间: 2024-01-23 21:11:24
品牌 Logo 应用领域
精工 - SEIKO 静态存储器内存集成电路
页数 文件大小 规格书
12页 133K
描述
256KX16 STANDARD SRAM, 85ns, PBGA48, TFBGA-48

S1M0W045B0J3 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA,针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:85 ns备用内存宽度:8
JESD-30 代码:R-PBGA-B48长度:10 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:48字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):3 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

S1M0W045B0J3 数据手册

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PF1068-02  
S1M0W045B0J3  
4M-bit Static RAM  
Super Low Voltage Operation and Low Current Consumption  
Access Time 85ns (2.3V)  
262,144 Words x 16-bit / 524,288 Words x 8-bit Asynchronous  
Wide Temperature Range  
DESCRIPTION  
The S1M0W045B0J3 is a 262,144 words x 16-bit (Word-mode) / 524,288 words x 8-bit (Byte-mode) asynchronous,  
random access memory on a monolithic CMOS chip. It is possible to select Word-mode or Byte-mode by CIO-  
pin: CIO=VDD for Word-mode and CIO=VSS for Byte-mode. Its very low standby power requirement makes it  
ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature  
of the memory requires no external clock and no refreshing circuit. It is possible to control the data width by the  
data byte control for Word-mode. 3-state output allows easy expansion of memory capacity. The temperature  
range of the S1M0W045B0J3 is from –40 to 85°C, and it is suitable for the industrial products.  
FEATURES  
Fast Access time ........................ 85ns (2.3V)  
Low supply current ..................... LL Version  
Completely static........................ No clock required  
Supply voltage............................ 2.3V to 3.0V  
3-state output with wired-OR capability  
Non-volatile storage with back-up batteries  
Package ..................................... S1M0W045B0J3  
TFBGA-48 pin (Tape CSP)  
BLOCK DIAGRAM  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
11  
11  
2048  
(2048)  
Memory Cell Array  
2048 x 2048  
A7  
A8  
A9  
(
)
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
SA  
128 x 16(256 x 8)  
Column Gate  
7
128  
(8)  
(256)  
CS1  
CS2  
CIO  
16(8)  
LB  
UB  
OE  
WE  
I/O Buffer  
I/O1  
I/O16  
( ): in case of Byte-mode  
Rev.1.1  
Rev.1.2  

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