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RTPXA270C0C208 PDF预览

RTPXA270C0C208

更新时间: 2024-09-18 03:48:55
品牌 Logo 应用领域
英特尔 - INTEL 外围集成电路
页数 文件大小 规格书
128页 1486K
描述
RISC Microprocessor, 32-Bit, 208MHz, CMOS, PBGA356

RTPXA270C0C208 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:FBGA, BGA356,24X24,20Reach Compliance Code:compliant
风险等级:5.8位大小:32
JESD-30 代码:S-PBGA-B356端子数量:356
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA356,24X24,20封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH电源:1.8,2.5,3.3 V
认证状态:Not Qualified速度:208 MHz
子类别:Microprocessors表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

RTPXA270C0C208 数据手册

 浏览型号RTPXA270C0C208的Datasheet PDF文件第2页浏览型号RTPXA270C0C208的Datasheet PDF文件第3页浏览型号RTPXA270C0C208的Datasheet PDF文件第4页浏览型号RTPXA270C0C208的Datasheet PDF文件第5页浏览型号RTPXA270C0C208的Datasheet PDF文件第6页浏览型号RTPXA270C0C208的Datasheet PDF文件第7页 
Intel® PXA270 Processor  
Electrical, Mechanical, and Thermal Specification  
Data Sheet  
High-performance processor:  
Low power:  
Intel XScale® microarchitecture with  
Intel® Wireless MMX™ Technology  
Wireless Intel Speedstep® Technology  
Less than 500 mW typical internal  
dissipation  
—7 Stage pipeline  
32 KB instruction cache  
32 KB data cache  
Supply voltage may be reduced to  
0.85 V  
Four low-power modes  
—2 KB “mini” data cache  
Extensive data buffering  
Dynamic voltage and frequency  
management  
256 Kbytes of internal SRAM for high  
speed code or data storage preserved  
during low-power states  
High-performance memory controller:  
Four banks of SDRAM: up to 104 MHz  
@ 2.5V, 3.0V, and 3.3V I/O interface  
High-speed baseband processor interface  
(Mobile Scalable Link)  
Six static chip selects  
Rich serial peripheral set:  
Support for PCMCIA and Compact  
Flash  
AC’97 audio port  
I2S audio port  
Companion chip interface  
Flexible clocking:  
USB Client controller  
USB Host controller  
USB On-The-Go controller  
CPU clock from 104 to 624 MHz  
Flexible memory clock ratios  
Frequency changes  
Three high-speed UARTs (two with  
hardware flow control)  
Functional clock gating  
FIR and SIR infrared communications  
port  
Additional peripherals for system  
connectivity:  
Hardware debug features — IEEE JTAG  
SD Card / MMC Controller (with SPI  
mode support)  
interface with boundary scan  
Hardware performance-monitoring  
Memory Stick card controller  
features with on-chip trace buffer  
Three SSP controllers  
Two I2C controllers  
Real-time clock  
Operating-system timers  
LCD Controller  
Four pulse-width modulators (PWMs)  
Keypad interface with both direct and  
matrix keys support  
Universal Subscriber Identity Module  
interface  
Most peripheral pins double as GPIOs  
Order Number 280002-006  

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