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PI6C2401 PDF预览

PI6C2401

更新时间: 2024-11-26 10:12:59
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器
页数 文件大小 规格书
4页 69K
描述
Phase-Locked Loop Clock Driver

PI6C2401 数据手册

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PI6C2401  
Phase-Locked Loop Clock Driver  
Product Features  
ProductDescription  
The PI6C2401 features a low-skew, low-jitter, phase-locked loop  
(PLL)clockdriver. ByconnectingthefeedbackCLK_OUToutput  
to the feedback FB_IN input, the propagation delay from the  
CLK_IN input to any clock output will be nearly zero.  
High-PerformancePhase-Locked-LoopClockDistributionfor  
Networking,ATM,100/134MHzRegisteredDIMMSynchro-  
nous DRAM modules for server/workstation/PC applications  
Zero Input-to-Output delay  
Lowjitter:Cycle-to-Cyclejitter ±100psmax.  
Application  
Ifthesystemdesignerneedsmorethan16outputswiththefeatures  
just described, using two or more zero-delay buffers such as  
PI6C2509Q,andPI6C2510Q,islikelytobeimpractical.Thedevice-  
to-device skew introduced can significantly reduce  
the performance. Pericom recommends the use of a zero-delay  
buffer and an eighteen output non-zero-delay buffer . As shown in  
Figure1,thiscombinationproducesazero-delaybufferwithallthe  
signal characteristics of the original zero-delay buffer, but with as  
manyoutputsasthenon-zero-delaybufferpart.Forexample,when  
combined with an eighteen output non-zero delay buffer, a system  
designer can create a seventeen-output zero-delay buffer.  
On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
Operatesat3.3VV  
CC  
Packaged in Plastic 8-pin SOIC Package (W)  
Pb-free and Green Available  
Wide range of Clock Frequencies  
Logic Block Diagram  
Product Pin Configuration  
CLK_IN  
PLL  
CLK_OUT  
1
CLK_IN  
8
7
6
5
FB_IN  
FB_IN  
AV  
CC  
V
CC  
2
3
4
8-Pin  
W
S
AGND  
GND  
S
CLK_OUT  
Feedback  
Control Input  
S
Output Source  
PLL  
PLL Shutdown  
1
0
N
Y
18 Output  
Non-Zero  
Delay  
Zero Delay  
Buffer  
PI6C2401  
CLK_OUT  
CLK_IN  
17  
Buffer  
Reference  
Clock  
Signal  
Figure 1. This Combination Provides Zero-Delay Between  
the Reference Clocks Signal and 17 Outputs  
PS8419C  
01/12/05  
1

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