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PI6C2404A-1I PDF预览

PI6C2404A-1I

更新时间: 2024-11-25 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟驱动器
页数 文件大小 规格书
6页 161K
描述
Clock IC | 2+2 Output Zero-Delay Clock Driver. 10 to 133 MHz

PI6C2404A-1I 数据手册

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PI6C2404A  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
The PI6C2404A is a PLL-based, zero-delay buffer, with the ability  
to distribute four outputs of up to 133 MHz at 3.3 V. Two banks of  
twooutputsexist, OUTA[1–2)andOUTB[1–2].  
Input to output delay, less than 200ps  
An external feedback pin is used to synchronize the outputs to the  
input; the relationship between loading of this signal and the other  
outputs determines the input-output delay.  
External feedback pin allows outputs to be synchronized  
to the clock input  
5V tolerant input*  
ThePI6C2404Aischaracterizedforbothcommercialandindustrial  
operation.  
Operatesat3.3VVDD  
Test mode allows bypass of the PLL for system testing  
purposes (e.g., IBIS measurements)  
Space-saving Packages:  
8-pin,150-milSOIC (W)  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
BlockDiagram  
PinConfiguration  
FB_IN  
CLKIN  
CLKIN  
OUTA1  
OUTA2  
GND  
8
7
6
5
1
2
3
4
FB_IN  
OUTA1  
OUTA2  
PLL  
8-Pin  
W
V
DD  
OUTB2  
OUTB1  
OUTB1  
OUTB2  
PinDescription  
Pin  
1
Signal  
Description  
CLKIN  
Input clock reference frequency (weak pull-down)  
Clock output, Bank A  
3.3V supply  
2, 3  
7
OUTA[1-2]  
VDD  
4
GND  
Ground  
5, 6  
8
OUTB[1-2]  
FB_IN  
Clock output, Bank B  
PLL feedback input  
PS8609  
04/10/02  
1

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