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PI6C2405-1HW PDF预览

PI6C2405-1HW

更新时间: 2024-11-26 19:58:11
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 542K
描述
PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8

PI6C2405-1HW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.7系列:6C
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mm最小 fmax:133 MHz
Base Number Matches:1

PI6C2405-1HW 数据手册

 浏览型号PI6C2405-1HW的Datasheet PDF文件第2页浏览型号PI6C2405-1HW的Datasheet PDF文件第3页浏览型号PI6C2405-1HW的Datasheet PDF文件第4页浏览型号PI6C2405-1HW的Datasheet PDF文件第5页浏览型号PI6C2405-1HW的Datasheet PDF文件第6页浏览型号PI6C2405-1HW的Datasheet PDF文件第7页 
PI6C2405/PI6C2409  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
The PI6C240x is a PLL based, zero-delay buffer, with the ability  
todistributefiveoutputsonPI6C2405,nineoutputsonPI6C2409of  
up to 133MHz at 3.3V. All the outputs are distributed from a single  
clock input CLKIN and output OUT0 performs zero delay by con-  
necting a feedback to PLL.  
Input to output delay, less than 200ps  
Internal feedback allows outputs to be synchronized  
to the clock input  
PI6C2409 has two banks of four outputs that can be controlled by  
theselectioninputs,SEL1&SEL2.Italsohasapowersparingfeature:  
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all  
outputs are referenced from CLKIN. PI6C2405 is an 8-pin version  
of PI6C2409 without selection inputs. PI6C240X is available in  
high drive and industrial environment versions.  
5V tolerant input*  
Operatesat3.3VVDD  
Space-saving Packages:  
150-milSOIC (W)  
173-milTSSOP (L)  
* CLKIN must reference the same voltage thresholds for the  
PLL to deliver zero delay skewing  
An internal feedback on OUT0 is used to synchronize the outputs  
to the input; the relationship between loading of this signal  
and the outputs determines the input-output delay.  
PI6C240X are characterized for both commercial and industrial  
operation  
BlockDiagram:PI6C2409  
PinConfigurationPI6C2409  
OUT0  
CLKIN  
OUTA1  
OUTA2  
16  
15 OUTA4  
1
2
3
4
5
6
7
8
OUT0  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
14  
13  
12  
11  
10  
9
OUTA3  
16-Pin  
W,L  
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
SEL1  
SEL2  
Decode  
Logic  
OUTB4  
OUTB3  
SEL1  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
PI6C2409 (-1, -1H)  
PinConfiguration:PI6C2405  
BlockDiagram:PI6C2405  
1
8
7
6
5
CLKIN  
OUT0  
OUT4  
2
3
4
8-Pin  
W,L  
OUT2  
OUT1  
V
DD  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
PLL  
GND  
OUT3  
CLKIN  
PI6C2405(–1, –1H)  
PSXXXX  
12/05/01  
1

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PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
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PI6C2405-1WIX PERICOM

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PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
PI6C2405-1WX PERICOM

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PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
PI6C2405A PERICOM

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Zero-Delay Clock Buffer