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PI6C2405-1HL PDF预览

PI6C2405-1HL

更新时间: 2024-11-27 10:20:23
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管
页数 文件大小 规格书
8页 229K
描述
PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 INCH, TSSOP-8

PI6C2405-1HL 数据手册

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PI6C2405  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
The PI6C2405 is a PLL based, zero-delay buffer, with the ability  
to distribute five outputs of up to 133MHz at 3.3V. All the outputs  
are distributed from a single clock input CLKIN and output OUT0  
performs zero delay by connecting a feedback to PLL.  
Input to output delay, less than 300ps  
Internal feedback allows outputs to be synchronized  
to the clock input  
5V tolerant input*  
An internal feedback on OUT0 is used to synchronize the outputs  
to the input; the relationship between loading of this signal  
and the outputs determines the input-output delay.  
PI6C2405ischaracterizedforbothcommercialandindustrialopera-  
tion  
Operatesat3.3VVDD  
Space-saving Packages:  
150-milSOIC (W)  
173-milTSSOP (L)  
* CLKIN must reference the same voltage thresholds for the  
PLL to deliver zero delay skewing  
BlockDiagram:PI6C2405  
PinConfiguration:PI6C2405  
1
2
3
4
8
7
6
5
CLKIN  
OUT2  
OUT1  
OUT0  
OUT4  
OUT0  
OUT1  
8-Pin  
W,L  
PLL  
CLKIN  
V
DD  
GND  
OUT3  
OUT2  
OUT3  
PI6C2405(–1, –1H)  
OUT4  
PinDescriptionforPI6C2405  
Pin  
Signal  
CLKIN  
Description  
1
Input clock reference frequency (weak pull-down)  
2, 3, 5, 7  
OUT[1-4]  
GND  
Clock outputs,  
3.3V supply  
Ground  
4
6
8
VDD  
OUT0  
Clock output, internal PLL feedback (weak pull-down)  
PS8592  
01/14/02  
1

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