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PI6C2402W PDF预览

PI6C2402W

更新时间: 2024-11-26 15:47:51
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
4页 136K
描述
PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8

PI6C2402W 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.47系列:6C
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:1最高工作温度:70 °C
最低工作温度:输出特性:SERIES-RESISTOR
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

PI6C2402W 数据手册

 浏览型号PI6C2402W的Datasheet PDF文件第2页浏览型号PI6C2402W的Datasheet PDF文件第3页浏览型号PI6C2402W的Datasheet PDF文件第4页 
PI6C2402  
Phase-Locked Loop Clock Driver  
ProductFeatures  
ProductDescription  
The PI6C2402 features a low-skew, low-jitter, phase-locked loop  
(PLL)clockdriver. ByconnectingthefeedbackCLK_OUToutput  
to the feedback FB_IN input, the propagation delay from the  
CLK_INinputtoanyclockoutputwillbenearlyzero.ThePI6C2402  
provides 2X CLK_IN on CLK_OUT output.  
2X CLK_INonCLK_OUT  
High-PerformancePhase-Locked-LoopClockDistribution  
for Networking, ATM, 100/134 MHz Registered DIMM  
Synchronous DRAM modules for server/workstation/  
PC applications  
Application  
Zero Input-to-Output delay  
Ifthe system designerneedsmore than16outputswiththe features  
just described, using two or more zero-delay buffers such as  
PI6C2509Q,andPI6C2510Q,islikelytobeimpractical.Thedevice-  
to-device skew introduced can significantly reduce the perfor-  
mance. Pericom recommends the use of a zero-delay buffer and an  
eighteen output non-zero-delay buffer. As shown in  
Figure1,thiscombinationproducesazero-delaybufferwithallthe  
signal characteristics of the original zero-delay buffer, but with as  
manyoutputsasthenon-zero-delaybufferpart.Forexample,when  
combined with an eighteen output non-zero delay buffer, a system  
designer can create a seventeen-output zero-delay buffer.  
Lowjitter:Cycle-to-Cyclejitter±100psmax.  
On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
Operatesat3.3VV  
CC  
Wide range of Clock Frequencies  
Package:  
Plastic8-pinSOICPackage(W)  
LogicBlockDiagram  
ProductPinConfiguration  
CLK_IN  
PLL  
CLK_OUT  
FB_IN  
2
S
1
CLK_IN  
AV  
8
7
6
5
FB_IN  
CC  
V
CC  
8-Pin  
W
2
3
4
AGND  
GND  
S
CLK_OUT  
Feedback  
ControlInput  
18 Output  
CLK_OUT Non-Zero  
S
Output Source  
PLL  
PLL Shutdown  
Zero Delay  
Buffer  
PI6C2402  
Delay  
Buffer  
17  
1
0
N
Y
Reference  
Clock  
CLK_IN  
Signal  
Figure1.ThisCombinationProvidesZero-DelayBetweenthe  
Reference Clocks Signal and 17 Outputs  
PS8418C  
08/02/02  
1

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