Datasheet > PI6C2402WEX

PI6C2402WEX

更新时间： 2024-11-26 15:47:51

品牌	Logo	应用领域
美台 - DIODES		驱动逻辑集成电路
页数	文件大小	规格书
4页	337K
描述
PLL Based Clock Driver,

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中文翻译

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技术参数
数据手册

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PI6C2402WEX 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.75	Is Samacsys：	N
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	Base Number Matches：	1

PI6C2402WEX 数据手册

PI6C2402

Phase-Locked Loop Clock Driver

Features

Description

The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop

(PLL) clock driver. By connecting the feedback CLK_OUT out-

put to the feedback FB_IN input, the propagation delay from the

CLK_INinputtoanyclockoutputwillbenearlyzero.ThePI6C2402

provides 2X CLK_IN on CLK_OUT output.

• Clock doubler

• High-Performance Phase-Locked-Loop Clock Distribution for

Networking, ATM, 100 MHz and 134 MHz Registered DIMM

Synchronous DRAM modules for server, workstation, and PC

applications

Applications

• Zero Input-to-Output delay

If the system designer needs more than 16 outputs with the fea-

tures just described, using two or more zero-delay buffers such

as the PI6C2509, and the PI6C2510, are likely to be impractical.

The device-to-device skew introduced can signiﬁcantly reduce

the performance. Pericom recommends the use of a zero-delay

buffer and an eighteen output non-zero-delay buffer. As shown in

Figure 1, this combination produces a zero-delay buffer with all the

signal characteristics of the original zero-delay buffer, but with as

many outputs as the non-zero-delay buffer part. For example, when

combined with an eighteen output non-zero delay buffer, a system

designer can create a seventeen-output zero-delay buffer.

• Cycle-to-Cycle jitter ≤ ±150ps max.

• On-chip series damping resistor at clock output drivers

for low noise and EMI reduction

• Operates at 3.3V V

• Packaging (Pb-free & Green available):

— 8-pin SOIC Package (W)

Pin Conﬁguration

Block Diagram

CLK_IN

FB_IN

CLK_IN

FB_IN

CLK_OUT

PLL

÷2

AGND

GND

CLK_OUT

Control Input

Feedback

Outputs Source

PLL

PLL Shutdown

Disabled

HIGH

LOW

CLK_IN

Enabled

18 Output

CLK_OUT Non-Zero

Zero Delay

Buffer

PI6C2402

Delay

Buffer

Reference

Clock

Signal

Figure 1. Zero-Delay Buffering Diagram

08-0298

PS8418I

11/13/08

12 3 4

中文翻译

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与PI6C2402WEX相关器件

型号	品牌	获取价格	描述	数据表
PI6C2402-WI	PERICOM	获取价格	6C SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 IN
PI6C2402WIE	PERICOM	获取价格	6C SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 IN
PI6C2402-WIE	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
PI6C2402-WIX	PERICOM	获取价格	6C SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 IN
PI6C2404A	PERICOM	获取价格	Zero-Delay Clock Buffer
PI6C2404A-1	PERICOM	获取价格	Zero-Delay Clock Buffer
PI6C2404A-1I	ETC	获取价格	Clock IC \| 2+2 Output Zero-Delay Clock Driver. 10 to 133 MHz
PI6C2404A-1W	PERICOM	获取价格	Zero-Delay Clock Buffer
PI6C2404A-1WE	PERICOM	获取价格	Zero-Delay Clock Buffer
PI6C2404A-1WEX	PERICOM	获取价格	暂无描述

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