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PI6C2404A-1 PDF预览

PI6C2404A-1

更新时间: 2024-11-26 02:50:59
品牌 Logo 应用领域
百利通 - PERICOM 时钟
页数 文件大小 规格书
6页 236K
描述
Zero-Delay Clock Buffer

PI6C2404A-1 数据手册

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PI6C2404A-1  
Zero-Delay Clock Buffer  
Features  
Description  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
ThePI6C2404A-1isaPLL-based,zero-delaybuffer,withtheability  
to distribute four outputs of up to 133 MHz at 3.3V. Two banks of  
twooutputsexist, OUTA[1–2]andOUTB[1–2].  
Input to output delay, less than 200ps  
An external feedback pin is used to synchronize the outputs to the  
input; the relationship between loading of this signal and the other  
outputs determines the input-output delay.  
External feedback pin allows outputs to be synchronized  
to the clock input  
5V tolerant input*  
ThePI6C2404A-1ischaracterizedforbothcommercialandindustrial  
operation.  
Operatesat3.3VVDD  
Test mode allows bypass of the PLL for system testing  
purposes (e.g., IBIS measurements)  
Space-saving Packaging (Pb-free and Green Available):  
8-pin,150-milSOIC (W)  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
BlockDiagram  
PinConfiguration  
FB_IN  
CLKIN  
CLKIN  
OUTA1  
OUTA2  
GND  
8
7
6
5
1
2
3
4
FB_IN  
OUTA1  
OUTA2  
PLL  
8-Pin  
W
V
DD  
OUTB2  
OUTB1  
OUTB1  
OUTB2  
PinDescription  
Pin  
1
Signal  
Description  
CLKIN  
Input clock reference frequency (weak pull-down)  
Clock output, Bank A  
3.3V supply  
2, 3  
7
OUTA[1-2]  
VDD  
4
GND  
Ground  
5, 6  
8
OUTB[1-2]  
FB_IN  
Clock output, Bank B  
PLL feedback input  
PS8609A  
01/13/05  
06-0036  
1

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