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PI6C2401WE PDF预览

PI6C2401WE

更新时间: 2024-11-26 10:12:59
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 69K
描述
Phase-Locked Loop Clock Driver

PI6C2401WE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
系列:6C输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:1最高工作温度:70 °C
最低工作温度:输出特性:SERIES-RESISTOR
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.885 mmBase Number Matches:1

PI6C2401WE 数据手册

 浏览型号PI6C2401WE的Datasheet PDF文件第2页浏览型号PI6C2401WE的Datasheet PDF文件第3页浏览型号PI6C2401WE的Datasheet PDF文件第4页 
PI6C2401  
Phase-Locked Loop Clock Driver  
Product Features  
ProductDescription  
The PI6C2401 features a low-skew, low-jitter, phase-locked loop  
(PLL)clockdriver. ByconnectingthefeedbackCLK_OUToutput  
to the feedback FB_IN input, the propagation delay from the  
CLK_IN input to any clock output will be nearly zero.  
High-PerformancePhase-Locked-LoopClockDistributionfor  
Networking,ATM,100/134MHzRegisteredDIMMSynchro-  
nous DRAM modules for server/workstation/PC applications  
Zero Input-to-Output delay  
Lowjitter:Cycle-to-Cyclejitter ±100psmax.  
Application  
Ifthesystemdesignerneedsmorethan16outputswiththefeatures  
just described, using two or more zero-delay buffers such as  
PI6C2509Q,andPI6C2510Q,islikelytobeimpractical.Thedevice-  
to-device skew introduced can significantly reduce  
the performance. Pericom recommends the use of a zero-delay  
buffer and an eighteen output non-zero-delay buffer . As shown in  
Figure1,thiscombinationproducesazero-delaybufferwithallthe  
signal characteristics of the original zero-delay buffer, but with as  
manyoutputsasthenon-zero-delaybufferpart.Forexample,when  
combined with an eighteen output non-zero delay buffer, a system  
designer can create a seventeen-output zero-delay buffer.  
On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
Operatesat3.3VV  
CC  
Packaged in Plastic 8-pin SOIC Package (W)  
Pb-free and Green Available  
Wide range of Clock Frequencies  
Logic Block Diagram  
Product Pin Configuration  
CLK_IN  
PLL  
CLK_OUT  
1
CLK_IN  
8
7
6
5
FB_IN  
FB_IN  
AV  
CC  
V
CC  
2
3
4
8-Pin  
W
S
AGND  
GND  
S
CLK_OUT  
Feedback  
Control Input  
S
Output Source  
PLL  
PLL Shutdown  
1
0
N
Y
18 Output  
Non-Zero  
Delay  
Zero Delay  
Buffer  
PI6C2401  
CLK_OUT  
CLK_IN  
17  
Buffer  
Reference  
Clock  
Signal  
Figure 1. This Combination Provides Zero-Delay Between  
the Reference Clocks Signal and 17 Outputs  
PS8419C  
01/12/05  
1

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