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NTB8N50

更新时间： 2024-09-16 15:46:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 开关脉冲晶体管
页数 文件大小 规格书
4页 73K
描述
Power Field-Effect Transistor, 8A I(D), 500V, 0.75ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, D2PAK-3

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中文翻译

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NTB8N50 技术参数

生命周期：Transferred包装说明：SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code：unknown风险等级：5.72
雪崩能效等级（Eas）：320 mJ外壳连接：DRAIN
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：500 V
最大漏极电流 (ID)：8 A最大漏源导通电阻：0.75 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：R-PSSO-G2
元件数量：1端子数量：2
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
极性/信道类型：N-CHANNEL最大脉冲漏极电流 (IDM)：28 A
认证状态：Not Qualified表面贴装：YES
端子形式：GULL WING端子位置：SINGLE
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

NTB8N50 数据手册

 浏览型号NTB8N50的Datasheet PDF文件第2页浏览型号NTB8N50的Datasheet PDF文件第3页浏览型号NTB8N50的Datasheet PDF文件第4页 
Preferred Device  
N–Channel Enhancement–Mode  
Silicon Gate  
http://onsemi.com  
TMOS POWER FET  
8 AMPERES  
This advanced TMOS E–FET is designed to withstand high energy  
in the avalanche and commutation modes. This new energy efficient  
design also offers a drain–to–source diode with a fast recovery time.  
Designed for low voltage, high speed switching applications in power  
supplies, converters and PWM motor controls, these devices are  
particularly well suited for bridge circuits where diode speed and  
commutating safe operating areas are critical and offer additional  
safety margin against unexpected voltage transients.  
500 VOLTS  
R
= 0.75 Ω  
DS(on)  
N–Channel  
D
New Features of TMOS 7  
• Ultra Low On–Resistance Provides Higher Efficiency  
• Reduced Gate Charge  
Features Common to TMOS 7 and TMOS E–FETS  
• Avalanche Energy Specified  
G
• Diode Characterized for Use in Bridge Circuits  
S
• I  
and V  
Specified at Elevated Temperature  
DS(on)  
DSS  
MARKING  
DIAGRAMS  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Drain–Source Voltage  
Symbol  
Value  
Unit  
4
V
DSS  
DGR  
500  
500  
Vdc  
Vdc  
Vdc  
2
D PAK  
CASE 418B  
STYLE 2  
NTB8N50  
YWW  
Drain–Gate Voltage (R  
= 1.0 MΩ)  
V
GS  
1
2
Gate–Source Voltage  
— Continuous  
3
V
20  
40  
GS  
— Non–Repetitive (t  
10 ms)  
p
V
GSM  
Drain — Continuous  
— Continuous @ 100°C  
I
I
8.0  
6.2  
28  
Adc  
YY, Y = Year  
WW, W = Work Week  
D
D
— Single Pulse (t  
10 µs)  
p
I
DM  
PIN ASSIGNMENT  
Total Power Dissipation  
Derate above 25°C  
P
142  
1.14  
Watts  
W/°C  
D
1
Gate  
Drain  
Operating and Storage Temperature  
Range  
T , T  
J stg  
–55 to  
150  
°C  
2
3
4
Source  
Single Drain–to–Source Avalanche  
E
AS  
320  
mJ  
Energy — Starting T = 25°C  
J
GS  
Drain  
(V  
= 100 Vdc, V  
= 10 Vdc,  
DD  
I
L
= 8.0 A, L = 10 mH, R = 25 Ω)  
G
Thermal Resistance  
— Junction–to–Case  
°C/W  
R
R
R
0.88  
62.5  
50  
ORDERING INFORMATION  
θJC  
θJA  
θJA  
— Junction–to–Ambient  
— Junction–to–Ambient (Note 1.)  
Device  
Package  
Shipping  
50 Units/Rail  
Maximum Lead Temperature for Soldering  
Purposes, 1/8″ from case for 10 seconds  
T
260  
°C  
L
2
D PAK  
NTB8N50  
2
1. When surface mounted to an FR4 board using the minimum recommended  
pad size.  
NTB8N50T4  
D PAK  
800 Tape & Reel  
Preferred devices are recommended choices for future use  
and best overall value.  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
June, 2000 – Rev. 0  
NTB8N50/D  
1234

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