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NLV14013BDTR2G PDF预览

NLV14013BDTR2G

更新时间: 2024-11-25 02:57:23
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 157K
描述
Dual Type D Flip-Flop

NLV14013BDTR2G 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.52系列:4000/14000/40000
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:2000000 Hz
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:5/15 V
Prop。Delay @ Nom-Sup:350 ns传播延迟(tpd):350 ns
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

NLV14013BDTR2G 数据手册

 浏览型号NLV14013BDTR2G的Datasheet PDF文件第2页浏览型号NLV14013BDTR2G的Datasheet PDF文件第3页浏览型号NLV14013BDTR2G的Datasheet PDF文件第4页浏览型号NLV14013BDTR2G的Datasheet PDF文件第5页浏览型号NLV14013BDTR2G的Datasheet PDF文件第6页浏览型号NLV14013BDTR2G的Datasheet PDF文件第7页 
MC14013B  
Dual Type D Flip-Flop  
The MC14013B dual type D flipflop is constructed with MOS  
Pchannel and Nchannel enhancement mode devices in a single  
monolithic structure. Each flipflop has independent Data, (D), Direct  
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary  
outputs (Q and Q). These devices may be used as shift register  
elements or as type T flipflops for counter and toggle applications.  
http://onsemi.com  
MARKING  
Features  
DIAGRAMS  
Static Operation  
14  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Logic EdgeClocked FlipFlop Design  
PDIP14  
P SUFFIX  
CASE 646  
MC14013BCP  
AWLYYWWG  
1
Logic state is retained indefinitely with clock level either high or  
low; information is transferred to the output only on the  
positivegoing edge of the clock pulse  
14  
SOIC14  
D SUFFIX  
CASE 751A  
14013BG  
AWLYWW  
Capable of Driving Two Lowpower TTL Loads or One Lowpower  
Schottky TTL Load Over the Rated Temperature Range  
PinforPin Replacement for CD4013B  
1
These Devices are PbFree, Halogen Free and are RoHS Compliant  
14  
14  
013B  
ALYW G  
G
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
TSSOP14  
DT SUFFIX  
CASE 948G  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
0.5 to +18.0  
Unit  
V
14  
V
DD  
DC Supply Voltage Range  
SOEIAJ14  
F SUFFIX  
CASE 965  
MC14013B  
ALYWG  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
T
A
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
WW, W = Work Week  
G or G  
= PbFree Package  
T
stg  
(Note: Microdot may be in either location)  
T
Lead Temperature  
(8Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
highimpedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
September, 2012 Rev. 9  
MC14013B/D  
 

NLV14013BDTR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC14013BDTR2G ONSEMI

完全替代

Dual Type D Flip−Flop
MC14013BDR2G ONSEMI

完全替代

Dual Type D Flip−Flop
MC14013BDG ONSEMI

完全替代

Dual Type D Flip−Flop

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