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NLV14040BDTR2G PDF预览

NLV14040BDTR2G

更新时间： 2024-11-24 12:18:51
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
9页 157K
描述
12-Bit Binary Counter

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中文翻译

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NLV14040BDTR2G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：ROHS COMPLIANT, PLASTIC, TSSOP-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：45 weeks风险等级：1.66
计数方向：UP系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
负载/预设输入：NO逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：1500000 Hz工作模式：ASYNCHRONOUS
湿度敏感等级：1位数：12
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
传播延迟（tpd）：3250 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：Counters最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：4.4 mm
Base Number Matches：1

NLV14040BDTR2G 数据手册

 浏览型号NLV14040BDTR2G的Datasheet PDF文件第2页浏览型号NLV14040BDTR2G的Datasheet PDF文件第3页浏览型号NLV14040BDTR2G的Datasheet PDF文件第4页浏览型号NLV14040BDTR2G的Datasheet PDF文件第5页浏览型号NLV14040BDTR2G的Datasheet PDF文件第6页浏览型号NLV14040BDTR2G的Datasheet PDF文件第7页 
MC14040B  
12-Bit Binary Counter  
The MC14040B 12−stage binary counter is constructed with MOS  
P−Channel and N−Channel enhancement mode devices in a single  
monolithic structure. This part is designed with an input wave shaping  
circuit and 12 stages of ripple−carry binary counter. The device  
advances the count on the negative−going edge of the clock pulse.  
Applications include time delay circuits, counter controls, and  
frequency−driving circuits.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
16  
1
• Fully Static Operation  
• Diode Protection on All Inputs  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
PDIP−16  
P SUFFIX  
CASE 648  
MC14040BCP  
AWLYYWWG  
• Capable of Driving Two Low−power TTL Loads or One  
Low−power Schottky TTL Load Over the Rated Temperature  
Range  
• Common Reset Line  
• Pin−for−Pin Replacement for CD4040B  
• These Devices are Pb−Free and are RoHS Compliant  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14040BG  
AWLYWW  
1
16  
14  
040B  
ALYW G  
G
TSSOP−16  
DT SUFFIX  
CASE 948F  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
16  
V
DD  
DC Supply Voltage Range  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14040B  
ALYWG  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
1
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
D
T
A
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
WW, W = Work Week  
G or G  
= Pb−Free Package  
T
stg  
(Note: Microdot may be in either location)  
T
Lead Temperature  
L
(8−Second Soldering)  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
April, 2013 − Rev. 10  
MC14040B/D  
 
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