Datasheet > NLV14043BDR2G

NLV14043BDR2G

更新时间： 2024-11-24 12:32:59

品牌	Logo	应用领域
安森美 - ONSEMI		锁存器
页数	文件大小	规格书
7页	143K
描述
CMOS MSI Quad RâS Latches

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NLV14043BDR2G 数据手册

MC14043B, MC14044B

CMOS MSI

Quad R−S Latches

The MC14043B and MC14044B quad R−S latches are constructed

with MOS P−Channel and N−Channel enhancement mode devices in a

single monolithic structure. Each latch has an independent Q output

and set and reset inputs. The Q outputs are gated through three−state

buffers having a common enable input. The outputs are enabled with a

logical “1” or high on the enable input; a logical “0” or low

disconnects the latch from the Q outputs, resulting in an open circuit at

the Q outputs.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC140xxBCP

AWLYYWWG

Features

• Double Diode Input Protection

• Three−State Outputs with Common Enable

• Outputs Capable of Driving Two Low−power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• These Devices are Pb−Free and are RoHS Compliant

SOIC−16

D SUFFIX

CASE 751B

140xxBG

AWLYWW

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

SOEIAJ−16

F SUFFIX

CASE 966

MC14043B

ALYWG

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

−0.5 to +18.0

Unit

DC Supply Voltage Range

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

= Year

I , I

in out

Input or Output Current

(DC or Transient) per Pin

± 10

WW, W = Work Week

= Pb−Free Indicator

Power Dissipation, per Package

(Note 1)

500

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

stg

Lead Temperature

(8−Second Soldering)

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V v (V or V ) v V

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Publication Order Number:

April, 2013 − Rev. 9

MC14043B/D

12 3 4 5 6 7

中文翻译

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NLV14044BDR2G	ONSEMI	获取价格	CMOS MSI Quad RâS Latches
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