Datasheet > NLV14069UBDTR2G

NLV14069UBDTR2G

更新时间： 2024-11-27 01:11:43

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	115K
描述
Hex Inverter

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中文翻译

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数据手册

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NLV14069UBDTR2G 数据手册

MC14069UB

Hex Inverter

The MC14069UB hex inverter is constructed with MOS P−channel

and N−channel enhancement mode devices in a single monolithic

structure. These inverters find primary use where low power

dissipation and/or high noise immunity is desired. Each of the six

inverters is a single stage to minimize propagation delays.

http://onsemi.com

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

SOIC−14

D SUFFIX

CASE 751A

SOEIAJ−14

F SUFFIX

CASE 965

TSSOP−14

DT SUFFIX

CASE 948G

• Triple Diode Protection on All Inputs

• Pin−for−Pin Replacement for CD4069UB

• Meets JEDEC UB Specifications

PIN ASSIGNMENT

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

IN 1

IN 6

OUT 1

IN 2

12 OUT 6

• These Devices are Pb−Free and are RoHS Compliant

IN 5

OUT 2

IN 3

MAXIMUM RATINGS (Voltages Referenced to V

)

OUT 5

IN 4

OUT 3

Symbol

Parameter

Value

−0.5 to +18.0

Unit

OUT 4

DC Supply Voltage Range

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

MARKING DIAGRAMS

I , I

Input or Output Current

(DC or Transient) per Pin

in out

Power Dissipation, per Package

(Note 1)

500

14069UG

AWLYWW

MC14069UB

ALYWG

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

stg

SOIC−14

SOEIAJ−14

Lead Temperature

(8−Second Soldering)

069U

ALYWG

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

TSSOP−14

WL, L

YY, Y

= Assembly Location

= Wafer Lot

= Year

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V ≤ (V or V ) ≤ V .

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

WW, W = Work Week

G or G

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

August, 2014 − Rev. 11

MC14069UB/D

12 3 4 5 6

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