MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
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MARKING
supply voltage, V . The input−signal high level (V ) can exceed the
DD
IH
V
DD
supply voltage for logic−level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS−to−TTL/DTL
converters (V = 5.0 V, V v 0.4 V, I ≥ 3.2 mA). Note that pins
DIAGRAMS
DD
OL
OL
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
16
1
PDIP−16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWWG
Features
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications
• V can exceed V
16
SOIC−16
D SUFFIX
CASE 751B
14049UBG
AWLYWW
IN
DD
1
• Improved ESD Protection on All Inputs
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
16
14
049UB
ALYW G
G
TSSOP−16
DT SUFFIX
CASE 948F
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
Unit
16
V
DD
DC Supply Voltage Range
−0.5 to +18.0
−0.5 to +18.0
V
V
SOEIAJ−16
F SUFFIX
CASE 966
V
in
Input Voltage Range
(DC or Transient)
MC14049UB
ALYWG
V
out
Output Voltage Range
(DC or Transient)
−0.5 to V
V
DD
1
+0.5
I
Input Current
(DC or Transient) per Pin
10
mA
mA
mW
in
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
I
Output Current
(DC or Transient) per Pin
+45
out
WW, W = Work Week
P
Power Dissipation, per Package (Note 1)
Plastic
SOIC
G or G
= Pb−Free Package
D
825
740
(Note: Microdot may be in either location)
T
Ambient Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
Storage Temperature Range
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
T
Lead Temperature (8−Second Soldering)
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V pin, only. Extra precautions
SS
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges
V
v V v 18 V and V v V v V are recommended.
SS
in
SS
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. 8
MC14049UB/D