Datasheet > NLV14042BDG

NLV14042BDG

更新时间： 2024-11-25 01:23:27

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	101K
描述
Quad Transparent Latch

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

NLV14042BDG 数据手册

MC14042B

Quad Transparent Latch

The MC14042B Quad Transparent Latch is constructed with MOS

P−channel and N−channel enhancement mode devices in a single

monolithic structure. Each latch has a separate data input, but all four

latches share a common clock. The clock polarity (high or low) used to

strobe data through the latches can be reversed using the polarity

input. Information present at the data input is transferred to outputs Q

and Q during the clock level which is determined by the polarity input.

When the polarity input is in the logic “0” state, data is transferred

during the low clock level, and when the polarity input is in the logic

“1” state the transfer occurs during the high clock level.

http://onsemi.com

SOIC−16

D SUFFIX

CASE 751B

Features

• Buffered Data Inputs

• Common Clock

PIN ASSIGNMENT

• Clock Polarity Control

• Q and Q Outputs

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

CLOCK

POLARITY

• This Device is Pb−Free and is RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to V

)

MARKING DIAGRAM

Symbol

Parameter

Value

−0.5 to +18.0

Unit

DC Supply Voltage Range

14042BG

AWLYWW

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

I , I

in out

Input or Output Current

(DC or Transient) per Pin

= Assembly Location

= Wafer Lot

Power Dissipation,

500

per Package (Note 1)

YY, Y

= Year

= Work Week

= Pb−Free Indicator

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

stg

Lead Temperature

(8−Second Soldering)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V ≤ (V or V ) ≤ V .

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Publication Order Number:

August, 2014 − Rev. 9

MC14042B/D

12 3 4 5 6

中文翻译

下载PDF

与NLV14042BDG相关器件

型号	品牌	获取价格	描述	数据表
NLV14042BDR2G	ONSEMI	获取价格	Quad Transparent Latch
NLV14043BDG	ONSEMI	获取价格	CMOS MSI Quad RâS Latches
NLV14043BDR2G	ONSEMI	获取价格	CMOS MSI Quad RâS Latches
NLV14044B	ONSEMI	获取价格	CMOS MSI Quad RâS Latches
NLV14044BDG	ONSEMI	获取价格	CMOS MSI Quad RâS Latches
NLV14044BDR2G	ONSEMI	获取价格	CMOS MSI Quad RâS Latches
NLV14049BDR2G	ONSEMI	获取价格	Hex Buffer
NLV14049UBDG	ONSEMI	获取价格	Hex Buffers
NLV14049UBDR2G	ONSEMI	获取价格	Hex Buffers
NLV14049UBDTR2G	ONSEMI	获取价格	六路逆变器

与NLV14042BDG相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

NLV14042BDG

NLV14042BDG 数据手册

与NLV14042BDG相关器件

与NLV14042BDG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

NLV14042BDG

NLV14042BDG 数据手册

与NLV14042BDG相关器件

与NLV14042BDG相关文章

您还可以找

您在本页遇到什么问题？