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NLV14021BDR2G PDF预览

NLV14021BDR2G

更新时间: 2024-11-07 01:21:11
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 107K
描述
8-Bit Static Shift Register

NLV14021BDR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.69
计数方向:RIGHT系列:4000/14000/40000
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:4000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):800 ns
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mmBase Number Matches:1

NLV14021BDR2G 数据手册

 浏览型号NLV14021BDR2G的Datasheet PDF文件第2页浏览型号NLV14021BDR2G的Datasheet PDF文件第3页浏览型号NLV14021BDR2G的Datasheet PDF文件第4页浏览型号NLV14021BDR2G的Datasheet PDF文件第5页浏览型号NLV14021BDR2G的Datasheet PDF文件第6页浏览型号NLV14021BDR2G的Datasheet PDF文件第7页 
MC14014B, MC14021B  
8-Bit Static Shift Register  
The MC14014B and MC14021B 8−bit static shift registers are  
constructed with MOS P−channel and N−channel enhancement mode  
devices in a single monolithic structure. These shift registers find primary  
use in parallel−to−serial data conversion, synchronous and asynchronous  
parallel input, serial output data queueing; and other general purpose  
register applications requiring low power and/or high noise immunity.  
http://onsemi.com  
Features  
Synchronous Parallel Input/Serial Output (MC14014B)  
Asynchronous Parallel Input/Serial Output (MC14021B)  
Synchronous Serial Input/Serial Output  
Full Static Operation  
SOIC−16  
D SUFFIX  
CASE 751B  
“Q” Outputs from Sixth, Seventh, and Eighth Stages  
Double Diode Input Protection  
PIN ASSIGNMENT  
P8  
Q6  
Q8  
P4  
P3  
P2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
DD  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
P7  
P6  
P5  
Q7  
Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
MC14014B Pin−for−Pin Replacement for CD4014B  
MC14021B Pin−for−Pin Replacement for CD4021B  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
D
C
S
P
1
V
P/S  
SS  
This Device is Pb−Free and is RoHS Compliant  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
MARKING DIAGRAM  
Symbol  
Parameter  
Value  
0.5 to +18.0  
Unit  
V
16  
V
DD  
DC Supply Voltage Range  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
140xxBG  
AWLYWW  
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
1
P
D
Power Dissipation, per Package  
(Note 1)  
500  
mW  
xx  
A
= Specific Device Code  
= Assembly Location  
WL, L  
YY, Y  
= Wafer Lot  
= Year  
T
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
WW, W = Work Week  
G
= Pb−Free Indicator  
T
Lead Temperature  
L
(8−Second Soldering)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V (V or V ) V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
July, 2014 − Rev. 9  
MC14014B/D  
 

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