Datasheet > NLV14027BDR2G

NLV14027BDR2G

更新时间： 2024-11-07 01:23:27

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	103K
描述
Dual J-K Flip-Flop

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中文翻译

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NLV14027BDR2G 数据手册

MC14027B

Dual J-K Flip-Flop

The MC14027B dual J−K flip−flop has independent J, K, Clock (C),

Set (S) and Reset (R) inputs for each flip−flop. These devices may be

used in control, register, or toggle functions.

Features

http://onsemi.com

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Swing Independent of Fanout

• Logic Edge−Clocked Flip−Flop Design

• Logic State is Retained Indefinitely with Clock Level Either High or

Low; Information is Transferred to the Output Only on the

Positive−Going Edge of the Clock Pulse

SOIC−16

D SUFFIX

CASE 751B

PIN ASSIGNMENT

• Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

• Pin−for−Pin Replacement for CD4027B

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• This Device is Pb−Free and is RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

−0.5 to +18.0

Unit

DC Supply Voltage Range

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

MARKING DIAGRAM

I , I

in out

Input or Output Current

(DC or Transient) per Pin

Power Dissipation, per Package

(Note 1)

500

14027BG

AWLYWW

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

stg

Lead Temperature

= Assembly Location

(8−Second Soldering)

YY, Y

= Wafer Lot

= Year

= Work Week

= Pb−Free Indicator

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V ≤ (V or V ) ≤ V .

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Publication Order Number:

August, 2014 − Rev. 8

MC14027B/D

12 3 4 5 6

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