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NL17SZ125_05 PDF预览

NL17SZ125_05

更新时间: 2024-11-06 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 141K
描述
Non-Inverting 3-State Buffer

NL17SZ125_05 数据手册

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NL17SZ125  
Non−Inverting 3−State Buffer  
The NL17SZ125 is a high performance noninverting buffer operating  
from a 1.65 V to 5.5 V supply.  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
Designed for 1.65 V to 5.5 V V Operation  
CC  
http://onsemi.com  
MARKING  
Overvoltage Tolerant Inputs and Outputs  
LVTTL Compatible Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
DIAGRAM  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current Substantially Reduces System  
M0 M G  
Power Requirements  
G
SC88A (SOT353)  
DF SUFFIX  
3State OE Input is ActiveLow  
Replacement for NC7SZ125  
Chip Complexity = 36 FETs  
PbFree Packages are Available  
CASE 419A  
M0 MG  
G
SOT553  
XV5 SUFFIX  
CASE 463B  
1
2
3
5
4
V
CC  
OE  
IN A  
GND  
M0 = Specific Device Code  
D
= Date Code  
= PbFree Package  
G
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
OUT Y  
Figure 1. Pinout (Top View)  
PIN ASSIGNMENT  
1
2
3
4
5
OE  
IN A  
GND  
OE  
IN A  
EN  
OUT Y  
OUT Y  
V
CC  
Figure 2. Logic Symbol  
FUNCTION TABLE  
A Input  
OE Input  
Y Output  
L
L
L
H
X
L
H
Z
H
X = Don’t Care  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
September, 2005 Rev. 5  
NL17SZ125/D  

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