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NL17SZ125_15 PDF预览

NL17SZ125_15

更新时间: 2024-11-03 01:18:27
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
12页 110K
描述
Non-Inverting 3-State Buffer

NL17SZ125_15 数据手册

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NL17SZ125  
Non-Inverting 3-State Buffer  
The NL17SZ125 is a high performance non−inverting buffer operating  
from a 1.65 V to 5.5 V supply.  
Features  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
www.onsemi.com  
MARKING DIAGRAMS  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Overvoltage Tolerant Inputs and Outputs  
LVTTL Compatible − Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
LVCMOS Compatible  
M0 MG  
SC−88A (SOT−353)  
DF SUFFIX  
G
24 mA Balanced Output Sink and Source Capability  
CASE 419A  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
3−State OE Input is Active−Low  
Replacement for NC7SZ125  
M0 MG  
SOT−553  
XV5 SUFFIX  
CASE 463B  
G
Chip Complexity = 36 FETs  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
5
1
5
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
1
M0 MG  
G
TSOP−5  
DT SUFFIX  
CASE 483  
OE  
EN  
OUT Y  
IN A  
Figure 1. Logic Symbol  
M
M
UDFN6  
1.0 x 1.0  
CASE 517BX  
1
1
SOT−953  
CASE 527AE  
M0 or F = Specific Device Code  
(F with 90 degree clockwise rotation)  
M
= Date Code  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may  
vary depending upon manufacturing location.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
June, 2015 − Rev. 18  
NL17SZ125/D  

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